Vector Load/Store Atomicity During Parallel Processor Execution
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Solution Overview
Problem
Existing processor designs fail to guarantee the atomicity of vector instructions due to multi-operation parallel execution mechanisms and the concurrent execution of barrier instructions, leading to inconsistent execution outcomes.
Innovation Solution
The method involves splitting vector load/store instructions into N operations, detecting events that could render the instruction non-atomic, and ensuring that either none or all of these operations produce processing effects to maintain atomicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vector instruction is split into multiple operations for parallel execution, then the execution efficiency is improved, but the atomicity of the vector instruction cannot be guaranteed
Solution Approach 1:
The patent applies preliminary action by establishing an atomic flag before executing the vector instruction. The flag is initialized to indicate atomic execution mode, and this pre-condition ensures that subsequent parallel operations will respect atomicity constraints. The flag serves as a preparatory mechanism that enables both parallel execution and atomicity guarantee.
Solution Approach 2:
The patent implements feedback through the atomic flag that is updated based on execution events. When an interrupt or exception occurs during the execution of split operations, the flag is checked and updated to reflect the atomicity status. This feedback mechanism allows the system to detect when atomicity has been compromised and take appropriate actions, such as rolling back partial results.
2Speed
If concurrent execution mechanism is introduced to improve instruction execution efficiency, then the processing speed is increased, but the atomicity of vector instructions is compromised
Solution Approach 1:
The atomic flag is set in advance before the concurrent execution begins, establishing the atomicity constraint as a pre-condition. This preliminary action ensures that all subsequent parallel operations execute under the guarantee of atomicity, allowing high-speed concurrent processing while maintaining reliability.
Solution Approach 2:
The atomic flag acts as an intermediary mechanism between the concurrent execution mechanism and the vector instruction execution. It mediates the conflict between parallel processing and atomicity requirements by providing a shared state that all concurrent operations must respect, enabling both speed and reliability to coexist.
3Productivity
If barrier instruction and vector instruction operations are processed concurrently, then the overall processing throughput is improved, but the atomicity guarantee of vector instructions is lost
Solution Approach 1:
The atomic flag is established before any concurrent operations including barrier instructions begin execution. This preliminary setting ensures that the atomicity guarantee is in place from the start, allowing barrier instructions and vector instructions to execute concurrently without compromising atomicity.
Solution Approach 2:
The atomic flag provides continuous feedback during concurrent execution of barrier and vector instructions. When any operation (including barrier instructions) interacts with the vector instruction execution, the flag is checked and updated accordingly. This feedback mechanism enables high throughput while maintaining atomicity through real-time monitoring and adjustment.
Data Source
AI summary
The present application provides an atomicity retaining method and a processor, and an electronic device. The method includes: generating N load/store operations from a vector load/store instruction, where N is a positive integer greater than or equal to 1; detecting whether there is an event during processing of the N load/store operations that renders the vector load/store instruction non-atomic; processing the N load/store operations; in a case that there is the event that renders the vector load/store instruction non-atomic, having none of the processing of the N load/store operations produce any processing effect, or having the N load/store operations all produce processing effects. The present application can realize retaining the atomicity of vector instructions.