Vector Processor Mask Dependency Reset for Faster Instruction Scheduling

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Solution Overview

Problem

In vector processors, the need to merge arithmetic operation results with existing data in destination registers is delayed due to unknown data dependency until mask values are read, leading to reduced processing performance.

Innovation Solution

A vector processor with a mask register, instruction decoder, scheduler, and dependency reset unit that sets and resets dependency information based on mask register states, allowing out-of-order execution of instructions without waiting for previous instructions to complete.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the scheduler waits for mask values to be read before determining data dependency, then data accuracy is ensured, but instruction execution speed decreases

Engineering Contradiction:
Improvedata accuracyVSAvoidinstruction execution speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The instruction decoder preliminarily determines data dependency by checking if the mask register is designated by the subsequent instruction, before the mask values are actually read. This preliminary judgment allows the scheduler to make execution decisions earlier, improving instruction execution speed while maintaining data accuracy through the all-set information verification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

All-set information acts as an intermediary mechanism that bridges the gap between early dependency determination and actual mask value reading. The all-set information serves as a proxy indicator that allows the scheduler to bypass the waiting period for mask value reading while ensuring data accuracy, effectively mediating between speed and accuracy requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the scheduler aligns instruction start timing with mask register setting completion, then data dependency is properly eliminated, but processing performance decreases

Engineering Contradiction:
Improvedata dependency eliminationVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary determination of data dependency elimination at the instruction decoding stage by checking all-set information, rather than waiting for mask register setting completion. This allows the scheduler to issue subsequent instructions earlier, improving processing performance while maintaining reliable data dependency elimination through the all-set information mechanism.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If the processor performs merge operations for all instructions, then data correctness is maintained, but power consumption increases

Engineering Contradiction:
Improvedata correctnessVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The processor applies different quality of merge operation based on local conditions: when all-set information is set, no merge operation is performed (simpler local handling), but when all-set information is not set, the full merge operation is executed (stricter local handling). This local differentiation maintains data correctness where needed while reducing power consumption where unnecessary merges would occur.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system discards the merge operation when all-set information indicates it is unnecessary, and recovers (performs the merge) only when data correctness requires it. This selective discarding and recovering of the merge operation optimizes the balance between data correctness and power consumption.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20250377889A1Vector processor and method of executing arithmetic operation in vector processor
Publication Date: 2025.12.11 FUJITSU LTD
  • US20250377889A1 patent drawing
  • US20250377889A1 patent drawing
  • US20250377889A1 patent drawing

AI summary

A vector processor includes a mask register configured to hold mask values, an instruction decoder configured to set dependency information included in instruction execution information when a decoded instruction is a subsequent instruction having data dependency with one or more previous instructions, and to set all-set information included in instruction execution information when a decoded instruction sets all of the mask values, a vector processing unit configured to execute vector arithmetic operations based on the instruction execution information, and to store in the data register a result of an arithmetic operation of a vector element corresponding to each mask value that is in a set state, and a dependency reset unit configured to reset the dependency information corresponding to a destination operand of the subsequent instruction and the mask register, when the all-set information is set for the mask register and the mask register is designated by the subsequent instruction.