Vector Matching Using Mask-and-Count Logic for IPv6 LPM
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Solution Overview
Problem
Current vector matching techniques in data communication networks, such as those used for Internet Protocol (IP) routing, face challenges with increased address lengths and traffic volumes, leading to higher memory requirements and latency due to the need for longer prefix matches, especially with the transition from IPv4 to IPv6, which uses 128-bit addresses.
Innovation Solution
A method and apparatus for calculating a composite index into a compressed address space based on a longest prefix match (LPM) using a combination of mask-and-count logic and variable shift registers, allowing for efficient storage and retrieval of data by compressing population counts and eliminating null and duplicate entries, thereby reducing memory usage and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address length is increased from IPv4 (32-bit) to IPv6 (128-bit), then addressing capacity is improved, but memory size and lookup latency increase
Solution Approach 1:
The patent divides the 128-bit IPv6 address into multiple smaller segments or strides (e.g., multiple 32-bit or 16-bit segments). Each segment is processed separately through hierarchical indexing, allowing the large address space to be broken down into manageable chunks that fit within available memory structures.
Solution Approach 2:
The patent introduces hierarchical indexing with multiple dimensions (e.g., first-level index, second-level index, third-level index) to organize the address space. Instead of a single linear memory structure, the address lookup transitions through multiple indexing levels, effectively adding dimensional organization to reduce memory requirements.
2Adaptability or versatility
If address length is increased from IPv4 (32-bit) to IPv6 (128-bit), then addressing capacity is improved, but lookup latency increases
Solution Approach 1:
The patent divides the 128-bit IPv6 address into multiple smaller segments or strides (e.g., multiple 32-bit or 16-bit segments). Each segment is processed separately through hierarchical indexing, allowing the large address space to be broken down into manageable chunks that fit within available memory structures.
Solution Approach 2:
The patent pre-computes and stores hierarchical index structures during memory initialization or updates. The multi-level indexing tables are prepared in advance, allowing runtime lookups to simply traverse the pre-built index hierarchy rather than performing complex searches on the full 128-bit address space.
3Adaptability or versatility
If memory size is increased to store larger address spaces, then addressing capacity is improved, but memory bandwidth consumption increases
Solution Approach 1:
The patent divides the 128-bit IPv6 address into multiple smaller segments or strides (e.g., multiple 32-bit or 16-bit segments). Each segment is processed separately through hierarchical indexing, allowing the large address space to be broken down into manageable chunks that fit within available memory structures.
Solution Approach 2:
The patent creates sparse index structures that only allocate memory for actually used address prefixes rather than allocating memory for all possible address combinations. This localized allocation means memory bandwidth is only consumed for relevant index entries that contain actual routing information.
4Quantity of substance
If sequential strides are used to parse addresses, then memory usage is reduced, but latency increases due to sequential processing
Solution Approach 1:
The patent divides the 128-bit IPv6 address into multiple smaller segments or strides (e.g., multiple 32-bit or 16-bit segments). Each segment is processed separately through hierarchical indexing, allowing the large address space to be broken down into manageable chunks that fit within available memory structures.
Solution Approach 2:
The patent combines multiple indexing operations into a single hierarchical lookup process. Rather than performing separate sequential searches for each address segment, the hierarchical index structure allows all segments to be processed together through a unified multi-level indexing mechanism, reducing the number of sequential memory accesses required.
Data Source
AI summary
An apparatus, system, and method is described for calculating a composite index into a customizable hybrid address space that is at least partially compressed to locate a longest prefix match (“LPM”) of a prefix string comprised of a plurality of multi-bit strides (“MBSs”). The device comprises: a mask-and-count logic for generating a base index into memory for a first MBS whose addresses are not compressed; a logical-shift apparatus that selectively uses a variable portion of the second MBS to generate an offset index from the given base index per an amount the second MBS addresses were actually compressed; and an add logic that adds the base index to the offset index to form the composite index that locates the LPM using a single access into memory. A compressed vector contains compression information of the second MBS in an information density format greater than a single bit to a single address.