Vector-by-Matrix Array Stack Interface for Compact Neural Computing
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Solution Overview
Problem
The lack of adequate hardware technology for high-performance artificial neural networks is hindered by the need for high computational parallelism and energy inefficiency in existing digital and analog circuits, particularly due to the bulkiness of CMOS-implemented synapses in neural networks.
Innovation Solution
Utilization of non-volatile memory arrays as synapses in artificial neural networks, allowing for continuous programming and precise tuning of memory cells, and implementing vector-by-matrix multiplication arrays to perform computations efficiently, reducing the need for separate multiplication and addition logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS analog circuits are used for neural networks, then computational functionality is achieved, but device size becomes bulky due to high number of neurons and synapses
Solution Approach 1:
The patent merges the synapse function directly into non-volatile memory cells, eliminating the need for separate CMOS analog circuit implementations of synapses. This integration reduces the overall device area while maintaining computational functionality by combining storage and computation in a single component.
Solution Approach 2:
The patent replaces traditional CMOS analog circuit mechanisms with non-volatile memory cell-based computation. This substitution uses the inherent properties of non-volatile memory (such as conductance changes) to perform synaptic functions, thereby reducing device size while maintaining adaptability.
2Productivity
If digital supercomputers or graphics processing unit clusters are used, then high computational parallelism is achieved, but energy efficiency deteriorates compared to biological networks
Solution Approach 1:
The non-volatile memory cells perform computation autonomously by utilizing their inherent conductance properties to multiply inputs and store weights simultaneously. This self-service capability eliminates the need for separate dedicated multiplication and addition circuits, reducing energy consumption while maintaining high computational parallelism.
Solution Approach 2:
The non-volatile memory cells serve multiple functions: they store weight values, perform multiplication operations, and enable parallel computation all within a single component. This multi-functionality achieves high computational parallelism without the energy overhead of separate dedicated circuits for each function.
3Measurement precision
If separate multiplication and addition logic circuits are used, then computational accuracy is maintained, but device complexity increases
Solution Approach 1:
The patent combines multiplication and addition operations into a single non-volatile memory cell array, where weights are stored in memory cells that simultaneously perform both functions through their conductance properties. This merging reduces circuit complexity while maintaining computational accuracy by eliminating the need for separate dedicated circuits.
Data Source
AI summary
In one example, a system comprises a first device; a first interface coupled to the first device and comprising one or more device control lines to identify a second device within a plurality of devices for which a communication is intended, the plurality of devices respectively containing vector-by-matrix multiplication arrays; and a stack comprising an interface circuit coupled to the first interface, the plurality of devices, and a second interface comprising lines compliant with a legacy standard, the second interface coupled between the interface circuit and the plurality of devices.