Vector-Matrix Linear Diffusion for Side-Channel Resistant Block Ciphers

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Solution Overview

Problem

Existing lightweight cryptography implementations for IoT devices are susceptible to side-channel attacks due to information leakage, particularly through cache latency, which compromises the security of sensitive data and cryptographic keys.

Innovation Solution

Implementing the linear diffusion layer of block ciphers using vector-matrix multiplication over a binary field, allowing for online computation and parallel evaluation of multiple computations to prevent timing attacks and cache latency attacks, without relying on precomputed tables, thereby enhancing side-channel resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If precomputed tables are used for the linear diffusion layer, then computation speed is improved, but side-channel leakage through cache latency occurs

Engineering Contradiction:

Improvecomputation speedVSAvoidside-channel leakage

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the precomputed tables from the system, replacing them with online computation. This eliminates the cache latency side-channel leakage that occurs when attackers observe memory access patterns, while maintaining computation speed through parallel evaluation techniques.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces parallel evaluation as an intermediary mechanism that computes the linear diffusion layer without requiring precomputed tables. By evaluating multiple computations simultaneously, it achieves speed comparable to table-based approaches while avoiding cache timing attacks.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If masking techniques are applied to protect against side-channel attacks, then security is improved, but computational overhead and complexity increase

Engineering Contradiction:

ImprovesecurityVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by designing the linear diffusion layer to be inherently resistant to cache timing attacks through online computation. This built-in resistance reduces or eliminates the need for additional masking techniques, thereby maintaining security without increasing computational complexity.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If lightweight cryptography algorithms are used in resource-constrained devices, then efficiency is improved, but resistance to side-channel attacks deteriorates

Engineering Contradiction:

ImproveefficiencyVSAvoidside-channel resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the computational parameters by transitioning from table-based computation to online computation with parallel evaluation. This parameter change maintains the efficiency required for resource-constrained devices while improving side-channel resistance by eliminating cache timing vulnerabilities.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10992470B2System and method for efficient and secure implementation of LS-Designs

Publication Date: 2021.04.27 LG ELECTRONICS INC

AI summary

The invention provides implementations of the block cipher in resource-constrained ARM devices that may be applied to both 32-bit and 64-bit versions of side-channel resistant and vectorized code and provides improves both efficiency and compactness by using of algorithmic techniques and features specific to a target platform. Specifically, an unprotected 32-bit implementation improves speed while reducing code size and a vectorized implementation improves performance and speed the implementation of block cipher.