Vector Matrix Multiplication With DSP Streaming Engine Prefetch

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in applications requiring predictable non-sequential input patterns for video encoding and other data processing tasks.

Innovation Solution

The implementation of a streaming engine within the DSP core that manages data streams with an address generation stage and data formatting stage, capable of handling multiple streams and supporting operations like vector-based matrix multiplication, improves memory bandwidth and data scheduling by directly supplying formatted data to the processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional memory access methods are used to load data registers, then memory bandwidth is limited and cache miss stalls occur, but processing speed and efficiency deteriorate

Engineering Contradiction:
Improveprocessing speedVSAvoidcache miss stalls
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The streaming engine pre-fetches and formats data from memory before the processor needs it, performing data preparation in advance. This eliminates wait time during processing by ensuring data is ready in the register file when required, thus resolving the contradiction between processing speed and cache miss stalls.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The streaming engine acts as an intermediary component between memory and the processor core. It handles data transfer and formatting operations, freeing the processor from memory management overhead and reducing cache miss impact on processing speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple processors with shared memory are used, then processing capability increases, but memory bandwidth and scheduling complexity worsen

Engineering Contradiction:
Improveprocessing capabilityVSAvoidmemory scheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system separates memory management functions into a dedicated streaming engine component, distinct from the processor core. This segmentation allows multiple processors to share memory without each processor needing to handle complex memory scheduling, as the streaming engine manages data flow independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The streaming engine autonomously manages data prefetching, formatting, and transfer operations without requiring complex inter-processor coordination. Each processor can independently utilize the streaming engine's services, simplifying memory scheduling while maintaining high productivity.

Inventive Principle:
Principle #25Self-service

3Productivity

If scalar operations are used for data processing, then operational simplicity is maintained, but processing efficiency and bandwidth to functional units deteriorate

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidscalar operations overhead
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The streaming engine combines multiple data preparation operations (prefetching, formatting, register loading) into a single integrated unit. This merging eliminates the overhead of separate scalar operations for each data preparation task, improving processing efficiency while maintaining operational simplicity through unified control.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12007904B2Method and apparatus for vector based matrix multiplication
Publication Date: 2024.06.11 TEXAS INSTRUMENTS INC
  • US12007904B2 patent drawing
  • US12007904B2 patent drawing
  • US12007904B2 patent drawing

AI summary

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.