Vector Matrix Multiplication with Streaming Engine Data Scheduling
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Solution Overview
Problem
Digital signal processors face challenges in efficiently performing real-time vector-based matrix multiplication due to memory bandwidth and scheduling constraints, which can impact the timely output of transformed data streams.
Innovation Solution
A processor architecture with a streaming engine that manages data streams, supports vector-based matrix multiplication, and includes separate instruction and data caches to enhance memory access and scheduling, allowing for efficient execution of vector matrix multiplication instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional scalar operations are used for matrix multiplication, then code simplicity is maintained, but processing speed and productivity deteriorate
Solution Approach 1:
The patent combines multiple scalar multiply-accumulate operations into a single vector matrix multiplication instruction. The vector unit executes one instruction that performs m×p multiply-accumulate operations simultaneously, merging what would otherwise require m separate scalar instructions into one unified operation, thereby achieving speedup without proportionally increasing control complexity
Solution Approach 2:
The patent transitions from scalar (1D) operations to vector (nD) operations by introducing vector registers and vector units. This dimensional change allows parallel execution of multiple operations within a single instruction cycle, transforming the processing paradigm from sequential scalar operations to concurrent vector operations while maintaining manageable instruction set complexity
2Speed
If separate instruction and data caches are implemented, then memory bandwidth and access speed improve, but device complexity increases
Solution Approach 1:
The patent divides the memory system into separate instruction cache and data cache segments. This segmentation allows independent optimization of each cache for its specific access patterns - instruction cache for code fetches and data cache for operand access - improving overall memory bandwidth and reducing contention while keeping each individual cache relatively simple
Solution Approach 2:
The separate cache structure provides universal support for both instruction fetching and data access operations. The same vector unit can efficiently access both instructions and data through the respective caches without requiring different hardware mechanisms, achieving multi-functionality with a unified architectural approach
3Productivity
If vector-based matrix multiplication is implemented, then processing efficiency improves, but requirements for memory bandwidth and scheduling increase
Solution Approach 1:
The patent loads matrix operands into vector registers in advance before the matrix multiplication operation begins. This preliminary action prefetches and stores the required data (m×n elements of matrix A and n×p elements of matrix B) into high-speed vector registers, reducing the actual memory bandwidth requirement during the compute-intensive multiplication phase
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.