Vector Memory Array Sorting With Bitonic Compare-and-Swap

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Solution Overview

Problem

Neural network accelerators (NNAs) lack a method to efficiently sort vector data, relying on non-deterministic algorithms like quicksort, which complicates scheduling and can lead to longer processing times than necessary.

Innovation Solution

A method utilizing the RISC-V vector extension to implement a bitonic sorting algorithm, generating new vectors for comparison and swapping elements based on a mask, allowing for deterministic sorting within a predetermined number of steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If quicksort algorithm is used for sorting vector data, then sorting can be performed with simple implementation, but the sorting time becomes non-deterministic and may be longer than necessary

Engineering Contradiction:
Improveease of implementationVSAvoidsorting time
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The patent changes the algorithmic parameters from quicksort to bitonic sort, transforming the sorting approach to achieve deterministic time complexity. This parameter change enables predictable performance by ensuring that the sorting operation always completes within a predetermined number of steps, eliminating the variability inherent in quicksort's best-case and worst-case scenarios.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The bitonic sorting algorithm segments the sorting process into distinct phases: comparison phases where pairs of elements are compared and swapped based on control signals, and permutation phases where elements are reordered. This segmentation allows each phase to be executed in a predetermined number of steps, contributing to overall deterministic timing.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If quicksort algorithm is used for sorting, then no additional hardware is required, but the processing time varies depending on data order and can exceed worst-case scenarios

Engineering Contradiction:
Improvehardware complexityVSAvoidtime predictability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces dynamic control signals that selectively enable or disable comparison and swap operations based on the current sorting state. These control signals are generated in a predetermined sequence, allowing the bitonic sort to adapt its operations dynamically while maintaining deterministic overall execution time. The dynamics principle is applied through the use of phase-dependent control logic that directs the sorting network's behavior.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces control signals as intermediaries that mediate between the sorting algorithm and the vector processing units. These control signals orchestrate the comparison and swap operations, ensuring that each phase completes in a predetermined number of steps. The intermediary control layer provides the deterministic timing framework while allowing flexible sorting operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If sorting is performed using CPU instead of vector extension, then vector processing capabilities are not utilized, but sorting can be performed with existing resources

Engineering Contradiction:
Improvesorting throughputVSAvoidprocessing architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the sorting function with the vector processing capabilities of the RISC-V extension. By implementing bitonic sort using vector instructions, the sorting operation leverages the parallel processing power of vector units while maintaining integration with the existing CPU architecture. This merging allows simultaneous utilization of vector hardware resources for sorting operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the vector processing unit multi-functional by enabling it to perform both traditional vector operations and sorting operations. The bitonic sorting algorithm is implemented using general vector instructions, allowing the same hardware resources to serve multiple purposes: data processing, data transformation, and data sorting. This universality increases productivity without requiring dedicated sorting hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12541366B2Sorting elements in a memory array by comparing element vectors
Publication Date: 2026.02.03 IMAGINATION TECH LTD
  • US12541366B2 patent drawing
  • US12541366B2 patent drawing
  • US12541366B2 patent drawing

AI summary

A method comprising comparing pairs of elements in an array. The method comprises generating two new vectors from an original array in memory, each comprising one part of each pair to be compared. The two new vectors are compared to generate a mask which indicates which of each pair of elements is less. Based on the mask, elements of the vectors can be swapped as necessary. This could be using a XOR algorithm or a merge algorithm. The vectors are then written back to the original array in memory. This process can be repeated on elements of an array as part of a bitonic sorting algorithm.