Completion Time Determination for Vector Memory Operations

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Solution Overview

Problem

Processor architectures that exploit data-level parallelism (DLP) face challenges in efficient instruction scheduling and execution due to variable completion times of vector memory operations, which hinder widespread adoption for general-purpose applications.

Innovation Solution

Incorporating a completion time determination circuit that calculates the completion time of vector memory operations based on TLB and cache accesses, allowing the issue circuit to align dependent operations with the availability of data from vector loads or store operations, thereby improving memory operation scheduling efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If vector memory operations are used to read/write vector data from non-consecutive memory locations, then data-level parallelism is enabled and memory access flexibility is improved, but completion time becomes variable and unknown at issue time, making instruction scheduling difficult

Engineering Contradiction:

Improvememory access flexibilityVSAvoidinstruction scheduling time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The completion time determination circuit performs preliminary calculation of completion time for vector memory operations at the time of issue, based on predicted number of TLB and cache accesses. This allows the issue circuit to schedule dependent operations in advance without waiting for actual completion, resolving the scheduling time loss problem while maintaining memory access flexibility.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses feedback mechanisms where the completion time determination circuit continuously monitors actual completion times and compares them with predicted values. This feedback loop allows for iterative improvement of scheduling accuracy and enables the issue circuit to refine its scheduling decisions based on actual performance data, addressing the variable completion time issue.

Inventive Principle:

Principle #23Feedback

2Adaptability or versatility

If variable number of cache accesses and TLB translations are used to execute vector loads/stores, then memory access adaptability is improved, but completion time becomes unknown at issue time, hindering efficient instruction scheduling

Engineering Contradiction:

Improvememory access adaptabilityVSAvoidinstruction scheduling efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The completion time determination circuit calculates predicted completion times at issue time based on the variable number of expected TLB and cache accesses. This preliminary action enables the issue circuit to schedule dependent operations efficiently without waiting for actual completion, thus improving instruction scheduling efficiency while maintaining memory access adaptability to variable access patterns.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts scheduling decisions based on actual completion times that may differ from predictions. The completion time determination circuit adapts its calculations based on runtime conditions, and the issue circuit dynamically modifies schedules to account for actual performance variations, resolving the contradiction between adaptability and scheduling efficiency.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If dependent operations are scheduled based on unknown completion time, then scheduling simplicity is maintained, but operation alignment with data availability is poor, reducing performance

Engineering Contradiction:

Improvescheduling complexityVSAvoidoperation scheduling performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The completion time determination circuit performs preliminary calculation of completion times at issue time, providing the issue circuit with advance knowledge of when data will be available. This eliminates the need for complex runtime scheduling adjustments while achieving optimal operation alignment with data availability, thus improving performance without significantly increasing scheduling complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The completion time determination circuit acts as an intermediary between the issue circuit and the execution units. It translates variable completion time characteristics into predictable scheduling information, enabling the issue circuit to make informed scheduling decisions that align operations with data availability while maintaining relatively simple scheduling logic.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9442734B2Completion time determination for vector instructions

Publication Date: 2016.09.13 APPLE INC

AI summary

In an embodiment, a processor may include a completion time determination circuit. The completion time determination circuit may be configured to receive one or more source operands of a vector memory operation used to produce the addresses of the vector elements accessed by the vector memory operation. The completion time determination circuit may be configured to determine a completion time for the vector memory operation (e.g. based on a number of TLB accesses, a number of cache accesses, and/or other aspects of the vector memory operation). The completion time determination circuit may provide the completion time to an issue circuit, which may use the completion time to schedule operations dependent on the vector memory operation, if any.