Vector Memory Permutation via Configuration Mediators
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Solution Overview
Problem
Current computing systems with vector architectures face inefficiencies in executing intra-vector operations, as they typically require rearranging or discarding data elements to perform different operations on non-consecutive elements within a single vector memory address, leading to increased computational resources and altered native storage structures.
Innovation Solution
The system divides program instructions into elemental sub-instructions, using configuration vector memories to permute and execute these instructions on non-consecutive data elements within a vector memory, allowing each element to undergo unique operations without altering the native storage structure, by employing a permutation processing layer with embedded pointers to group and manipulate vector elements in stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If elements in vector memories are rearranged to align elements for composition, then intra-vector operations can be executed, but extra processing steps are added and the native storage structure is altered
Solution Approach 1:
The patent introduces configuration vector memories as intermediary structures that store permutation indices. These configuration memories act as mediators between the native vector memory storage structure and the execution units, enabling intra-vector operations without directly rearranging the native storage structure. The configuration memories contain pointers that redirect access to the correct elements, thus facilitating complex operations while preserving the original storage layout.
Solution Approach 2:
The patent segments the vector processing functionality by separating configuration data from execution data. Configuration vector memories store permutation and selection information separately from the actual data elements in native vector memories. This segmentation allows the system to maintain the native storage structure while adding configuration-layer control to enable intra-vector operations.
2Stability of the object's composition
If the native storage structure of vector memories is maintained, then data integrity is preserved, but brute-force composition of every element combination wastes significant computational resources
Solution Approach 1:
The patent performs preliminary action by pre-loading configuration values into configuration vector memories before execution. These configuration values contain pre-computed permutation indices and selection criteria that guide the execution units. By preparing this configuration data in advance, the system avoids wasting computational resources during actual execution, as the execution units can directly follow the pre-determined configuration rather than computing all possible combinations.
Solution Approach 2:
The configuration vector memories provide feedback mechanisms that guide the execution units on which specific element combinations to process. The configuration data acts as feedback information that tells the execution units exactly which elements to compose, eliminating the need for brute-force trial of all possible combinations and thereby reducing wasted computational resources.
3Productivity
If configuration values are loaded from data memory and program memory into configuration vector memories, then intra-vector operations can be executed efficiently, but additional memory access operations are required
Solution Approach 1:
The system performs preliminary action by loading configuration values into configuration vector memories before the main execution phase. This pre-loading allows the execution units to operate efficiently during the computation phase without repeated memory access delays, as the configuration data is already resident in the configuration vector memories during execution.
Data Source
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AI summary
A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.