Vector Operand Bitsize Control via Exception Level Limits
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Solution Overview
Problem
Data processing systems supporting vector operations face challenges in accommodating varying vector operand bit sizes across different exception levels, leading to potential data leakage and inconsistent performance due to fixed architecture limitations, which hinders software portability and operational efficiency.
Innovation Solution
The system employs decoder circuitry and processing circuitry that respond to vector operand bit size dependent instructions, using programmable limit values across a hierarchy of exception levels to control vector processing operations, ensuring that vector operand bit sizes are managed within defined limits, allowing software to constrain and determine optimal bit sizes dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed vector operand bit size is defined in the architecture, then the system structure is simple and easy to implement, but the system cannot accommodate varying vector operand bit sizes across different exception levels, leading to data leakage and inconsistent performance
Solution Approach 1:
The patent implements dynamic vector operand bit size control by introducing exception level states (EL0-EL3) with programmable limit values (PLV0-PLV3). The decoder circuitry dynamically selects the appropriate bit size limit based on the current exception level state, allowing the system to adapt vector operand bit sizes from 128 to 1024 bits depending on the operational context and privilege level.
Solution Approach 2:
The patent applies local quality by assigning different vector operand bit size limits to different exception levels. Each exception level (EL0, EL1, EL2, EL3) has its own programmable limit value, allowing software at each level to constrain vector operations to appropriate bit sizes for that level, preventing data leakage while enabling optimal performance for each exception level's requirements.
2Productivity
If software is modified to work with specific hardware configurations, then operational efficiency is optimized for that hardware, but software portability across different hardware configurations is reduced
Solution Approach 1:
The patent creates a universal interface for vector operand bit size control that works across all exception levels and hardware configurations. The programmable limit values and exception level mechanism provide a standardized way for software to control vector operations regardless of the underlying hardware capabilities, allowing the same software to run efficiently on different hardware configurations without modification.
Solution Approach 2:
The patent enables parameter changes by allowing software to dynamically adjust the vector operand bit size limit through the programmable limit values associated with each exception level. This allows software to optimize vector processing parameters (bit sizes of 128, 256, 512, or 1024 bits) based on the specific hardware configuration and operational requirements, maintaining both portability and efficiency.
3Productivity
If vector operand bit size is increased to improve parallel operation, then processing throughput is enhanced, but the risk of data leakage between exception levels increases
Solution Approach 1:
The patent applies preliminary anti-action by establishing programmable limit values for each exception level before vector operations are executed. The decoder circuitry checks the current exception level's PLV setting before allowing vector operations, preventing data leakage by constraining operations to appropriate bit sizes in advance, rather than attempting to correct issues after they occur.
Solution Approach 2:
The patent implements feedback through the exception level mechanism, where the current exception level state (EL0-EL3) provides feedback to the decoder circuitry about the appropriate bit size limit to apply. This feedback loop ensures that vector operations automatically adapt to the current privilege level and security context, maintaining data isolation while enabling efficient parallel processing within the constrained bit size.
Data Source
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AI summary
A data processing system (2) includes processing circuitry (18) and decoder circuitry (14) for decoding program instructions and controlling the processor circuitry. The decoder circuitry is responsive to a vector operand bit size dependant instruction executed within a selected exception level state of a hierarchy of exception level states to control the processing circuitry to perform processing with a vector operand bit size governed by a limiting value of the vector operand bit size associated with the currently selected exception level state, any programmable limit value set for an exception level state closer to a top exception level state within the hierarchy and the implemented limit.