Vector Packet Forwarding with Learned Node Bypass
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Solution Overview
Problem
Existing network apparatus face challenges in balancing the need for intelligent, flexible software solutions with high-performance hardware capabilities, particularly in handling increasing network data and bandwidth demands, leading to resource overutilization and inefficiencies in CPU usage.
Innovation Solution
Implement a method for vector packet processing that includes a learning-and-recording mode and an optimized acceleration mode, utilizing entrance and exit labeling-and-categorizing plug-in units to manage packet forwarding paths, allowing for efficient use of intermediate nodes based on learned packet characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software optimization and acceleration methods are used (combining VPP with DPDK and SR-IOV), then network functionality intelligence is improved, but CPU resource occupation remains high and acceleration effect is limited
Solution Approach 1:
The forwarding path is segmented into multiple intermediate nodes, each responsible for specific packet processing tasks. The system divides packet processing into different stages (learning-and-recording mode and optimized acceleration mode), allowing parallel processing and reducing the burden on single CPU cores.
Solution Approach 2:
The system performs preliminary actions by learning packet forwarding patterns in advance during the learning-and-recording mode. This pre-processing enables the system to store optimized forwarding paths before actual data traffic arrives, so that subsequent packets can be forwarded using pre-computed optimal routes without requiring complex real-time decisions.
2Productivity
If hardware acceleration using ASIC or FPGA NIC is implemented, then processing capability is improved, but cost increases significantly
Solution Approach 1:
The system creates virtual copies of hardware acceleration capabilities through software-based intermediate nodes that simulate specialized processing functions. Instead of requiring physical ASIC or FPGA hardware for each function, the system uses software intermediaries that replicate the behavior of dedicated hardware, providing similar performance benefits at lower cost.
Solution Approach 2:
The intermediate nodes are designed with multi-functionality, capable of performing various packet processing tasks (filtering, routing, transformation) that would traditionally require different specialized hardware components. This universal approach allows a single software-based infrastructure to replace multiple specialized hardware devices, reducing overall system cost while maintaining processing capability.
3Reliability
If packets pass through all intermediate nodes in the forwarding path, then processing accuracy is maintained, but forwarding performance and resource utilization deteriorate
Solution Approach 1:
The forwarding path is made dynamic rather than static. The system learns packet characteristics and traffic patterns, then dynamically adjusts the forwarding path to bypass unnecessary intermediate nodes. This dynamic adaptation allows the system to maintain processing accuracy for packets that require full inspection while enabling fast-forwarding for packets that can safely skip certain nodes, optimizing the balance between reliability and performance.
Solution Approach 2:
The system implements feedback mechanisms where the learning-and-recording mode continuously monitors packet processing outcomes and uses this information to refine forwarding decisions. By analyzing which intermediate nodes are essential for maintaining processing accuracy and which can be safely bypassed, the system develops optimized forwarding paths that preserve reliability while improving performance through selective node skipping.
Data Source
AI summary
A method for forwarding a vector packet processing (VPP) is applicable to a forwarding path. The forwarding path includes an interface entrance, a data plane development kit (DPDK) input end, an entrance labeling-and-categorizing plug-in unit, one or more intermediate nodes, a Tx output end, an exit labeling-and-categorizing plug-in unit, and an interface exit. The vector packet processing forwarding method includes: executing a learning-and-recording mode for a preceding packet to obtain a learning result, and in the learning-and-recording mode, having the preceding packet entirely pass through the forwarding path; and executing an optimized acceleration mode for a subsequent packet, and in the optimized acceleration mode, based on the learning result, having the subsequent packet detour at least one intermediate node of the one or more intermediate nodes in the forwarding path.