Vector PLL Frequency Synthesizer for Wideband Fine Tuning
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Solution Overview
Problem
Conventional frequency synthesizers face challenges in finely setting frequencies over a broad band while maintaining low noise and broad frequency entrainment range, with complex circuit construction and increased noise due to digital/analog converter switching noise.
Innovation Solution
A novel frequency synthesizer architecture that uses vector extraction and inverse vector multiplication to achieve precise frequency setting, employing a one-stage PLL with frequency division ratio adjustment and digital processing to minimize noise and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency division ratio N is increased to set frequency finely, then frequency resolution is improved, but noise becomes large due to elongation of delay in loop
Solution Approach 1:
The patent divides the frequency synthesis function into multiple independent synthesizers, each handling a specific frequency band with its own PLL. This segmentation allows each PLL to operate with a moderate frequency division ratio (N ≤ 1000) while collectively covering a broad frequency range with fine resolution, avoiding the noise problem of excessively large N in a single PLL.
Solution Approach 2:
The patent introduces a new dimension of frequency control by using multiple PLLs operating in parallel at different frequency bands, rather than relying on a single PLL with extremely high division ratio. This dimensional approach (multiple bands × multiple PLLs) achieves fine frequency resolution without the harmful delay elongation in a single loop.
2Adaptability or versatility
If multistage frequency synthesizers are combined to cover broad frequency band with fine resolution, then frequency range and resolution are improved, but circuit construction becomes complicated and number of parts increases
Solution Approach 1:
The patent segments the broad frequency band into multiple manageable bands, with each band handled by a dedicated PLL synthesizer. This segmentation makes the overall complex system decomposable into simpler, independent modules, each with standardized circuit construction, thereby reducing overall system complexity despite covering a broad frequency range.
Solution Approach 2:
Each PLL synthesizer in the patent is designed as a universal module that can be configured for different frequency bands through programmable frequency division ratios. This multi-functionality allows the same basic circuit architecture to serve multiple frequency bands, reducing the need for specialized circuits for each band and simplifying overall construction.
3Measurement precision
If multistage frequency synthesizers are combined to achieve fine frequency setting, then frequency resolution is improved, but noise is increased
Solution Approach 1:
By segmenting the frequency synthesis into multiple independent PLLs, each operating at moderate division ratios, the patent eliminates the need for extremely high N values that cause noise. Each segment (PLL) operates quietly with N ≤ 1000, and the combined system achieves fine resolution through the coordinated operation of these low-noise segments.
4Object-generated harmful factors
If frequency division ratio N is limited to about 1000 to reduce noise, then noise is reduced, but frequency resolution deteriorates
Solution Approach 1:
The patent compensates for the limited division ratio (N ≤ 1000) by adding another dimension of frequency control through multiple PLLs operating in parallel. The combined frequency resolution is achieved through the product of the number of PLLs and the division ratio of each, allowing fine resolution without requiring any single PLL to have excessively high N.
Data Source
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AI summary
An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. As s specific solving means, a sinusoidal signal of an output frequency of a voltage-controlled oscillator is subjected to orthogonal detection, a vector rotating at the differential frequency (speed)between the output frequency and the frequency of the frequency signal used for the detection is created, and the frequency of a vector when the output frequency of the voltage-controlled oscillator is equal to a set value is calculated in advance. The voltage signal corresponding to the difference between the frequency of the vector and the calculated frequency is fed back to the voltage-controlled oscillator when the voltage-controlled oscillator is driven, and PLL is formed so that the difference is equal to zero. Accordingly, the output frequency of the voltage-controlled oscillator is adjusted to the set frequency when PLL is locked. After the difference between both the frequencies is increased after PLL is locked, the set value is integrated by the integrating circuit portion and added to the control voltage.