Vector Processor Predicate Fault Masking for Runtime Dependency Resolution
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Solution Overview
Problem
Existing processor architectures face challenges in vectorizing loops due to loop-carried data dependencies and memory-address aliasing, which limits the performance benefits of data-level parallelism, as compilers cannot conclusively determine runtime dependencies during compilation.
Innovation Solution
A processor architecture that executes vector instructions with optional predicate vectors, allowing for dynamic determination of parallelism at runtime by masking faults and updating result vectors based on fault-status registers, enabling parallel execution of loop iterations based on runtime conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compilers perform static analysis during compilation to determine parallelism, then compilation time is reduced and simplicity is maintained, but runtime dependencies cannot be conclusively determined limiting vectorization
Solution Approach 1:
The patent applies preliminary action by performing static analysis during compilation to identify potential parallelism opportunities and generate vectorized code, while also preparing runtime mechanisms (dependency detection hardware, fault-status registers) to resolve uncertainties that cannot be determined at compile time. This allows the system to attempt vectorization upfront while having fallback mechanisms ready.
Solution Approach 2:
The patent introduces intermediary mechanisms including dependency detection hardware, fault-status registers, and predicate vectors that act as mediators between the compiled code and runtime execution. These intermediaries capture runtime dependency information that was unavailable during compilation, enabling the system to safely vectorize loops by detecting and handling dependencies that emerge during execution.
2Speed
If vector instructions are executed without runtime dependency checking, then execution speed increases, but incorrect results may occur due to undetected dependencies
Solution Approach 1:
The patent applies skipping by allowing vector instructions to execute rapidly through loop iterations without immediate dependency checking, rushing through computations at high speed. Dependency detection is performed selectively using predicate vectors and fault-status registers only when necessary, rather than checking every operation, thus maintaining high execution speed while ensuring correctness when dependencies exist.
Solution Approach 2:
The patent implements feedback mechanisms where execution results are monitored and fed back to dependency detection hardware and fault-status registers. This feedback loop allows the system to detect dependencies that arise during execution and adjust the predicate vectors accordingly, ensuring that subsequent vector operations maintain correctness while preserving overall execution efficiency.
3Manufacturing precision
If comprehensive runtime dependency detection is implemented, then vectorization accuracy improves, but processor complexity increases
Solution Approach 1:
The patent applies segmentation by dividing dependency detection into separate, specialized components: fault-status registers for capturing dependency states, predicate vectors for representing per-element execution conditions, and dependency detection hardware for analyzing runtime dependencies. This segmentation allows each component to perform its specific function efficiently without requiring the entire system to be overly complex.
Solution Approach 2:
The patent applies local quality by implementing dependency detection and predicate evaluation at the element level rather than requiring global analysis of entire vectors. Each element's dependency status is tracked independently through predicate vectors, allowing the system to achieve high vectorization accuracy for individual elements while maintaining overall processor efficiency and managing complexity through localized rather than centralized detection.
Data Source
AI summary
The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a vector instruction that optionally receives a predicate vector (which has N elements) as an input. The processor then executes the vector instruction. In the described embodiments, executing the vector instruction causes the processor to generate a result vector. When generating the result vector, if the predicate vector is received, for each element in the result vector for which a corresponding element of the predicate vector is active, otherwise, for each element of the result vector, the processor determines element positions for which a fault was masked during a prior operation. The processor then updates elements in the result vector to identify a leftmost element for which a fault was masked.