Vector Predicate Tracking for Streaming Engine Loop Control

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Solution Overview

Problem

Digital signal processors face challenges in efficiently managing memory bandwidth and scheduling for real-time data processing, particularly in handling valid and invalid data elements within data vectors, which can lead to inefficiencies in instruction execution and data processing.

Innovation Solution

An autonomous streaming engine is integrated into the digital signal processor to manage data streams, including a mechanism to record valid data elements within data vectors, allowing the processor to use predicate information to control instruction execution and optimize data movement, thereby improving memory bandwidth and scheduling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the processor executes instructions on all data elements in a data vector, then complete data processing is achieved, but processing efficiency decreases due to invalid data elements

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidinstruction execution time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts and processes only the valid data elements from the data vector by using a streaming engine to track valid elements and generate predicate information. This allows the processor to take out and process only the necessary valid elements while ignoring invalid ones, thereby improving data processing efficiency and reducing instruction execution time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by differentiating between valid and invalid data elements within the data vector. By assigning different processing qualities to different elements (valid elements are processed, invalid elements are skipped), the system optimizes overall processing efficiency without compromising the integrity of valid data processing.

Inventive Principle:
Principle #3Local quality

2Productivity

If the processor manages memory bandwidth without predicate tracking, then simple memory management is maintained, but memory bandwidth utilization is inefficient

Engineering Contradiction:
Improvememory bandwidth utilizationVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by using the streaming engine to track valid data elements and generate predicate information before the processor executes instructions. This advance preparation of predicate information allows the processor to efficiently manage memory bandwidth by knowing in advance which data elements are valid, thereby improving memory bandwidth utilization without significantly increasing memory management complexity.

Inventive Principle:
Principle #10Preliminary action

3Speed

If the processor handles real-time data without autonomous streaming engine, then system complexity is reduced, but real-time processing capability is insufficient

Engineering Contradiction:
Improvereal-time processing speedVSAvoidprocessor architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces an autonomous streaming engine as an intermediary component between the data source and the processor. This streaming engine tracks valid data elements, generates predicate information, and supplies it to the processor, thereby enhancing real-time processing speed while isolating the complexity of predicate tracking from the main processor architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11507520B2Tracking streaming engine vector predicates to control processor execution
Publication Date: 2022.11.22 TEXAS INSTRUMENTS INC
  • US11507520B2 patent drawing
  • US11507520B2 patent drawing
  • US11507520B2 patent drawing

AI summary

In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.