Energy Scalable Vector Processing Core Cluster Architecture
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Solution Overview
Problem
The use of multiple processor platforms in integrated systems leads to interoperability issues, increased system configuration costs, and inefficient energy consumption due to code differences and varying performance requirements, making it difficult to dynamically control computing capacity and energy usage.
Innovation Solution
An energy scalable vector processing apparatus with a parallel core processor structure that includes a cache memory and a cluster cache controller, allowing core clusters to share cache memory and adjust the number of active core clusters based on computing demands, thereby controlling energy consumption and computing capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple processor platforms are used in integrated systems to meet varying performance requirements, then application performance requirements can be satisfied, but interoperability between platforms degrades and system configuration costs increase
Solution Approach 1:
The patent implements a universal processor architecture where a single processor platform can functionally replace multiple dedicated processors. The processor is designed with a unified instruction set and memory architecture that allows it to perform various functions previously requiring separate dedicated hardware platforms, thereby improving interoperability while maintaining adaptability to different performance requirements.
Solution Approach 2:
The patent merges the functions of multiple dedicated processors into a single integrated processor platform. By combining what were previously separate processor architectures into one unified system, the patent eliminates code differences and interoperability issues while still能够满足 various performance requirements through software configuration and core activation.
2Productivity
If dedicated processors are used for different applications, then performance requirements can be met, but system configuration costs increase due to code differences and inability to reuse data and code
Solution Approach 1:
The processor is designed as a universal platform that can execute various applications through a unified instruction set architecture. This eliminates the need for multiple dedicated processors with different instruction sets, thereby reducing system configuration costs while maintaining the ability to meet different performance requirements through software optimization and core activation.
Solution Approach 2:
The patent utilizes parameter changes in the form of dynamic core activation and frequency adjustment to meet different performance requirements. Instead of requiring different hardware architectures for different applications, the system changes operational parameters (which cores are active, what frequencies are used) to adapt to varying performance demands, thereby reducing configuration costs.
3Productivity
If processors with high operating frequency and wide hardware area are used, then high performance is achieved, but energy consumption increases
Solution Approach 1:
The patent divides the processor into multiple independent cores that can be activated or deactivated based on application requirements. This segmentation allows the system to achieve high performance when needed by activating multiple high-frequency cores, while reducing energy consumption during lower-performance periods by deactivating unnecessary cores, thus resolving the contradiction between performance and energy consumption.
Solution Approach 2:
The processor implements dynamic frequency adjustment and core activation/deactivation capabilities. The operating frequency and active core count are dynamically changed based on application demands, allowing the system to optimize the balance between performance and energy consumption in real-time rather than operating at fixed high performance levels continuously.
4Use of energy by moving object
If processors with low frequency and small hardware area are used, then energy efficiency is improved, but computing capacity is reduced
Solution Approach 1:
The processor is segmented into multiple cores that can be independently activated. When high computing capacity is needed, multiple low-frequency cores are activated in parallel, collectively providing the required computing capacity while maintaining energy efficiency. When lower capacity is sufficient, fewer cores are activated, reducing energy consumption further.
Solution Approach 2:
The patent combines multiple low-frequency cores to achieve high computing capacity when needed. Instead of relying on a single high-frequency processor that would consume more energy continuously, the system merges the computational power of multiple energy-efficient low-frequency cores, achieving both energy efficiency and high computing capacity through parallel operation.
Data Source
AI summary
A core cluster includes a cache memory, a core, and a cluster cache controller. The cache memory stores and provides instructions and data. The core accesses the cache memory or a cache memory provided in an adjacent core cluster, and performs an operation. The cluster cache controller allows the core to access the cache memory when the core requests memory access. The cluster cache controller allows the core to access the cache memory provided in the adjacent core cluster when the core requests a clustering to the adjacent core cluster. The cluster cache controller allows a core provided in the adjacent core cluster to access the cache memory when the core receives a clustering request from the adjacent core cluster.