Vector Processing Unit Shared Scheduler Queue Optimization
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Solution Overview
Problem
Existing vector processing systems require separate hardware and pipeline control logic for mask and vector operations, leading to increased cost, complexity, and latency.
Innovation Solution
A vector processing unit with a shared scheduler queue and shared pipeline control logic, where both mask and vector type instructions are stored in the same queue and controlled by the same logic, using a shared source register bit field to index into both mask and vector register files.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware and pipeline control logic are used for mask and vector operations, then operational reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines separate mask and vector scheduler queues into a single unified scheduler queue, and merges separate mask and vector pipeline control logic into shared pipeline control logic. This consolidation reduces device complexity and hardware cost while maintaining the ability to reliably execute both mask and vector operations through a unified control structure.
Solution Approach 2:
The unified scheduler queue and shared pipeline control logic are designed to handle both mask-type instructions and vector-type instructions universally. The same hardware structures perform multiple functions by processing different instruction types, eliminating the need for dedicated separate hardware paths while maintaining operational reliability for both operation types.
2Manufacturing precision
If separate hardware structures are used for mask and vector operations, then operational precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges separate hardware structures for mask and vector operations into unified structures. The single scheduler queue and shared pipeline control logic reduce manufacturing complexity and cost by eliminating redundant hardware components while preserving the precision needed for both mask and vector operations through unified control mechanisms.
3Reliability
If separate pipeline control logic is used for mask and vector instructions, then processing reliability is improved, but latency increases
Solution Approach 1:
By merging separate pipeline control logic into shared pipeline control logic that handles both mask and vector instructions, the patent reduces the number of separate processing paths and control stages. This consolidation eliminates redundant control overhead and reduces latency while maintaining processing reliability through unified control of both instruction types in the same pipeline.
Solution Approach 2:
The shared pipeline control logic universally handles both mask-type and vector-type instructions through the same control path, eliminating the need for separate control logic sequences. This multi-functional approach reduces the total number of control cycles and latency while ensuring reliable processing of both instruction types through consistent control mechanisms.
Data Source
AI summary
A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.