Vector Processor Fault Masking for Loop Dependency Handling
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Solution Overview
Problem
Existing vector processing systems face challenges in vectorizing loops due to loop-carried data dependencies and memory aliasing, which limits the extent of parallelism that can be exploited, requiring extensive manual recoding and hindering widespread adoption.
Innovation Solution
A processor architecture that supports non-faulting and first-faulting instructions for vector operations, allowing conditional masking of faults and dynamic switching between scalar and vector execution based on runtime conditions, enabling parallelism without requiring complete parallelism determination at compile-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector processing is used to exploit data-level parallelism, then processing speed and performance are improved, but the requirement for manual recoding increases due to loop-carried data dependencies and memory aliasing
Solution Approach 1:
The patent changes the fault handling parameter from traditional faulting to non-faulting and first-faulting modes. This allows the vector processor to continue execution despite potential memory aliasing issues, automatically handling dependencies without requiring manual recoding of loops. The processor dynamically adjusts fault masking behavior based on the specific instruction and runtime conditions.
Solution Approach 2:
The vector processor performs self-service by automatically detecting and handling loop-carried data dependencies and memory aliasing through its non-faulting and first-faulting instruction mechanisms. The processor monitors execution conditions and dynamically switches between scalar and vector modes without external intervention, eliminating the need for extensive manual recoding while maintaining high performance.
2Productivity
If complete parallelism determination is required at compile-time, then vectorization can be achieved, but the complexity of manual recoding increases significantly
Solution Approach 1:
The patent introduces dynamic fault masking capabilities that allow the processor to adapt parallelism determination at runtime rather than requiring complete determination at compile-time. The non-faulting and first-faulting instructions enable the processor to dynamically switch between vector and scalar execution based on actual runtime conditions, reducing manual recoding complexity while maintaining vectorization benefits.
Solution Approach 2:
The processor performs preliminary fault masking setup through special instructions (non-faulting and first-faulting) that prepare the execution environment for potential dependencies. This preliminary action allows the processor to attempt vectorized execution with built-in protection mechanisms, rather than requiring all dependency analysis to be completed beforehand through complex manual recoding.
3Reliability
If traditional faulting behavior is used in vector operations, then correctness is maintained, but performance is reduced due to frequent fault exceptions
Solution Approach 1:
The patent applies local quality by implementing different fault handling behaviors for different elements within a vector operation. The first-faulting instruction masks faults for all elements except the first, while non-faulting masks faults for specific elements based on runtime conditions. This localized approach maintains correctness where needed while improving performance by avoiding unnecessary fault exceptions in other elements.
Solution Approach 2:
The processor uses partial fault masking where not all elements require strict fault checking. The first-faulting mode applies fault masking to all but the first element, and non-faulting mode applies selective masking based on conditions. This partial action approach maintains sufficient correctness while improving performance by reducing the number of fault exceptions compared to traditional universal faulting behavior.
Data Source
AI summary
The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation).