Vector Processor Linear Interpolation via Parallel Memory Retrieval
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Solution Overview
Problem
Current techniques for performing linear interpolation in vector processors are inefficient, leading to slow calculations in applications like wireless communications, where data processing requires evaluating a function for data sample values using lookup tables and interpolation between table entries.
Innovation Solution
The use of vector processors with vector addressable memory architectures allows for simultaneous retrieval of discrete data points from memory, enabling efficient linear, bi-linear, and tri-linear interpolation calculations across multiple dimensions by leveraging hardware instructions or software operations to perform interpolation in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lookup table techniques are used for linear interpolation, then memory usage is reduced by storing only coarse subset entries, but calculation speed deteriorates due to sequential processing requirements
Solution Approach 1:
The patent segments the interpolation calculation into multiple independent parallel operations by dividing the data stream into multiple channels, each performing interpolation simultaneously. This allows the system to maintain compact lookup tables while achieving high-speed parallel processing, resolving the contradiction between memory efficiency and calculation speed.
Solution Approach 2:
The patent transitions from one-dimensional sequential interpolation to multi-dimensional parallel interpolation by utilizing multiple processing dimensions simultaneously. This dimensional expansion enables the system to perform multiple interpolations in parallel without increasing lookup table size, thereby improving speed while maintaining memory efficiency.
2Measurement precision
If linear interpolation is performed between LUT entries for data values between table entries, then accuracy is improved by calculating intermediate values, but processing time increases due to multiple calculation steps
Solution Approach 1:
The patent performs preliminary organization of lookup table data into a structure that enables direct parallel access. By pre-arranging the data in a format suitable for simultaneous retrieval across multiple dimensions, the system eliminates sequential access delays while maintaining the accuracy benefits of interpolation between table entries.
Solution Approach 2:
The patent ensures continuous parallel processing by maintaining multiple interpolation operations active simultaneously across different data channels. This continuous parallel action eliminates idle time between calculations while preserving the precision of interpolation methods, thereby reducing overall processing time without sacrificing accuracy.
Data Source
AI summary
Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.