Vector Processor Circuit Dynamic Pipeline Scheduling
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Solution Overview
Problem
Machine learning algorithms, such as deep neural networks, require high computational complexity, making them inefficient on general-purpose CPUs, and existing hardware acceleration techniques do not effectively manage the dynamic sequences of vector processing operations required for these algorithms.
Innovation Solution
The development of a processor circuit with a scheduler that dynamically configures vector processing pipelines to perform sequences of vector operations on input vectors, using a selector circuit and scheduler circuit to optimize the order and timing of operations without pre-specified scheduling information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed vector processing pipeline is used, then the device complexity is reduced, but the adaptability to different machine learning algorithms deteriorates
Solution Approach 1:
The vector processing pipeline is made dynamically reconfigurable through a scheduler circuit that can change the sequence of vector processing operations at runtime. The selector circuit enables dynamic selection of different operation sequences based on the specific machine learning algorithm being executed, allowing the system to adapt to various algorithms while maintaining a unified hardware structure.
2Productivity
If vector processing operations are executed in a predetermined sequence, then the device complexity is reduced, but the productivity for machine learning algorithms deteriorates
Solution Approach 1:
The scheduler circuit is pre-configured with multiple valid sequences of vector processing operations. Before executing a machine learning algorithm, the appropriate pre-defined sequence is selected and configured, allowing the pipeline to be optimized for the specific algorithm without requiring complex real-time scheduling decisions during execution.
3Use of energy by moving object
If general-purpose CPU is used for machine learning algorithms, then the device complexity is reduced, but the energy efficiency deteriorates
Solution Approach 1:
The vector processing pipeline is designed as a universal hardware accelerator that can execute multiple types of machine learning algorithms through reconfigurable operation sequences. The same physical hardware structure serves multiple functions by dynamically adjusting the sequence of vector processing operations, eliminating the need for separate specialized hardware for each algorithm type.
Data Source
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Figure 4A
AI summary
A processor circuit is provided that includes an input terminal and an output terminal, a plurality of vector processor operation circuits, a selector circuit coupled to the input terminal, the output terminal, and each of the vector processor operation circuits, and a scheduler circuit adapted to control the selector circuit to configure a vector processing pipeline comprising zero, one or more of the vector processor operation circuits in any order between the input terminal and the output terminal.