Vector Processor Real-Complex Multiplication Circuit
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Solution Overview
Problem
Digital signal processors face challenges in efficiently performing real-complex multiplications, particularly in digital signal vector processors, which require significant resources and power, and often result in higher latency and area costs due to the need for multiple parallel multipliers and complex circuitry.
Innovation Solution
A digital signal processor instruction set is introduced that includes specific instructions and a calculation circuit to perform real-complex multiplications using only P/2 arithmetic circuits, allowing for real-valued inputs to be processed as adjacent elements in a vector, reducing the need for duplicate calculations and circuitry, and enabling real-complex and complex-complex multiplications with reduced resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If real-complex multiplication is performed using conventional complex multiplication instructions, then the multiplication can be completed in a single clock cycle, but four parallel multipliers are required which increases power consumption and resource usage
Solution Approach 1:
The patent merges the real-complex multiplication operation with a complex multiplication operation by processing both operations simultaneously using the same hardware resources. The real-complex multiplication is performed by treating the real scalar as a complex number with zero imaginary part, allowing both operations to share the same multiplier array and control logic, thereby reducing power consumption while maintaining single-cycle latency
Solution Approach 2:
The patent implements a universal multiplication unit that can perform both complex-complex multiplication and real-complex multiplication using the same hardware circuitry. The multiplication unit is designed to accept complex operands and can be configured to perform real-complex multiplication by setting the imaginary part of one operand to zero, eliminating the need for separate dedicated hardware for different multiplication types
2Productivity
If real-complex multiplication uses P parallel multipliers for P element-wise operations, then single-cycle completion is achieved, but device area and resource occupancy increase significantly
Solution Approach 1:
The patent merges adjacent multiplication operations by processing pairs of complex elements simultaneously. Instead of requiring P separate multipliers for P element-wise real-complex multiplications, the design uses P/2 complex multipliers that process two elements each by exploiting the mathematical relationship between adjacent complex numbers and their conjugates, thereby reducing device area while maintaining throughput
Solution Approach 2:
The patent segments the P-element vector into P/2 pairs of adjacent complex elements. Each pair is processed by a single complex multiplier that computes both real-complex multiplication results simultaneously by utilizing the symmetry properties of complex conjugates, effectively dividing the computational workload to reduce the number of required hardware units
3Reliability
If duplicate calculations are performed for real-complex multiplication using complex multiplication instructions, then correct results are obtained, but resource efficiency decreases due to redundant operations
Solution Approach 1:
The patent extracts and utilizes only the necessary computational components for real-complex multiplication from the full complex multiplication operation. By recognizing that the imaginary part of one operand is zero, the design extracts and performs only the two essential multiplication operations (real×real and real×imaginary) while eliminating the redundant operations, thereby maintaining correctness while improving resource efficiency
Data Source
AI summary
According to an aspect, a digital signal processor obtains a program instruction, selects a first real valued input or a second real valued input as a given real valued input (the first and second real valued inputs organized as adjacent elements of a first input vector), depending on an instruction type. The processor performs an arithmetic operation on the selected real valued input to provide a real valued result, and provides a first real valued output and a second real valued output during a first operation cycle (organized as adjacent elements of a second output vector).The real valued result is provided as the first real valued output and as the second real valued output, depending on the instruction type, and the second output vector is a real valued second output vector for real-complex multiplication with a complex valued third vector.