Vector Processor Shuffle Unit for Data Access Flexibility
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Solution Overview
Problem
Existing vector processors face inefficiencies in processing speed and power consumption due to redundant data shuffling operations and the need for separate instructions for each cycle, leading to longer program codes.
Innovation Solution
A vector processor design with multiple register files, a shuffle unit, and a shuffle control unit that performs data shuffling and parallel operations without re-storing, using multiplexers to route data to corresponding SIMD lanes and controlling the process based on input instructions to optimize data usage and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is shuffled and re-stored in the vector register file for each cycle, then data can be accessed in different orders, but power consumption increases significantly
Solution Approach 1:
The shuffle unit performs data shuffling in advance before the execution unit processes the data. By pre-organizing the data in the required order and providing it directly to the execution unit, the system eliminates the need for repeated shuffle-and-restore cycles, thereby reducing power consumption while maintaining data access flexibility
Solution Approach 2:
The shuffle operation is extracted from the register file and implemented as a separate shuffle unit. This dedicated unit handles all shuffling operations externally, allowing the register file to simply store and retrieve data without performing complex shuffle operations, thus reducing power consumption
2Ease of operation
If separate instructions are used for each shuffling operation, then precise data control is achieved, but program code length increases
Solution Approach 1:
The shuffle unit is designed to handle multiple different shuffling patterns using a single unified hardware structure. By incorporating configurable multiplexers and control logic, the same shuffle unit can perform various shuffle operations (different data orders, different cycle patterns) without requiring separate hardware or instructions for each case, thus reducing program code length while maintaining precise data control
Solution Approach 2:
The shuffle unit employs dynamic control through control signals that can be adjusted based on the required shuffling pattern. The multiplexers within the shuffle unit can be dynamically configured to route data in different orders, allowing a single instruction to control variable shuffling behavior rather than requiring separate instructions for each pattern
3Reliability
If data is shuffled and re-stored repeatedly for each cycle, then correct data is provided to execution units, but processing speed decreases
Solution Approach 1:
The shuffle unit performs data shuffling in advance before the execution unit processes the data. By pre-organizing the data in the required order and providing it directly to the execution unit, the system eliminates the need for repeated shuffle-and-restore cycles, thereby reducing power consumption while maintaining data access flexibility
Solution Approach 2:
The register files continuously provide data to the shuffle unit, which in turn continuously provides shuffled data to the execution unit without interruption. This continuous data flow eliminates idle cycles caused by repeated store-and-fetch operations, maintaining processing continuity and speed while ensuring data accuracy through the dedicated shuffle unit
Data Source
AI summary
A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.