Vector Processor Sliding Window Parallelism
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Solution Overview
Problem
Current vector processor architectures face inefficiencies in processing high-resolution images due to the computational intensity of sliding window operations, which are common in image processing algorithms, leading to suboptimal performance and hardware utilization.
Innovation Solution
A logic circuit and method for performing configurable sliding window operations in a vector processor, allowing parallel selection and arithmetic processing of data elements based on a pattern, with each group shifted relative to the previous, and including multipliers and adders for efficient arithmetic operations, enabling flexible implementation of one-dimensional, two-dimensional, or higher-dimensional filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential sliding window operations are used for high-resolution image processing, then processing completeness is maintained, but processing speed and productivity deteriorate due to computational intensity
Solution Approach 1:
The filter is divided into multiple patterns, and the image processing is segmented into parallel operations across multiple vector registers. Each vector register processes a portion of the data simultaneously, breaking down the computationally intensive sequential operation into manageable parallel segments that can be executed concurrently.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to multi-dimensional parallel processing by utilizing multiple vector registers and patterns. Data elements are processed across multiple dimensions (different vector registers, different patterns, different shift amounts) simultaneously, dramatically increasing processing throughput for high-resolution images.
2Productivity
If more data elements are processed in parallel, then processing efficiency improves, but hardware resource utilization and power consumption worsen
Solution Approach 1:
The patent applies partial action by processing only the necessary portions of data in parallel using selective patterns and shift amounts. Not all vector registers or all data elements are processed simultaneously in every operation cycle, allowing the system to achieve useful parallelism while avoiding the power consumption overhead of full-system parallel operation.
Solution Approach 2:
The system dynamically changes parameters such as shift amounts and pattern selections to optimize the balance between parallelism and power consumption. By adjusting these parameters, the processor can adapt the degree of parallel execution to match the computational requirements of different filtering operations, achieving high efficiency without excessive power usage.
3Adaptability or versatility
If a fixed filter structure is used, then hardware implementation is simpler, but adaptability to different image processing algorithms deteriorates
Solution Approach 1:
The patent implements a universal filter structure where the same logic circuit can perform multiple different filtering operations by changing the pattern and shift amount parameters. The system is designed to be multi-functional, supporting various image processing algorithms (corner detection, edge detection, Gaussian filtering, etc.) without requiring separate dedicated hardware for each algorithm, thus achieving high adaptability with controlled complexity.
Solution Approach 2:
The filter structure is made dynamic through configurable patterns and shift amounts that can be changed during operation. Rather than a static fixed filter, the system can adapt its configuration to match different algorithm requirements, allowing the same hardware to efficiently implement various filtering operations with different window sizes, strides, and data element selections.
Data Source
AI summary
A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.


