Vector Processor Parallel Data Stream Alignment

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Solution Overview

Problem

Existing technologies are inefficient in processing heterogeneous data streams due to serial or sequential processing methods, which are slow and inadequate for handling high bandwidth data rates in modern communication systems.

Innovation Solution

A vector processor with parallel processing units and a grouping memory that writes and reads data samples into and from multiple bins simultaneously, utilizing a bit-level Benes network for efficient conversion between heterogeneous and homogeneous data formats.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If serial or sequential processing methods are used to separate or combine data streams, then processing simplicity is maintained, but processing speed and efficiency deteriorate

Engineering Contradiction:
Improvedata processing speedVSAvoidprocessing architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor is divided into multiple processing elements (PEs), each capable of independently processing different data streams. This segmentation enables parallel processing of multiple homogeneous streams simultaneously, dramatically improving data processing speed while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from sequential single-dimension processing to parallel multi-dimension processing by organizing PEs in a spatial array that can simultaneously handle multiple data streams. This dimensional transformation allows the processor to exploit spatial parallelism, achieving high throughput without proportionally increasing control complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If parallel processing units are implemented to accelerate data processing, then processing speed improves, but device complexity increases

Engineering Contradiction:
Improvedata processing rateVSAvoidprocessor structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Each processing element is designed as a universal unit capable of handling multiple data stream formats and compression schemes. This multi-functionality reduces the need for specialized hardware for each stream type, allowing parallel processing acceleration while controlling overall device complexity through standardized reusable components

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically configures processing parameters such as data stream format, compression scheme, and PE assignment based on incoming data characteristics. This parameter adaptability allows the parallel processor to optimize performance for different scenarios without requiring fixed complex hardware for every possible data type

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If heterogeneous data streams with different formats and compression schemes are processed, then data format flexibility is improved, but processing efficiency deteriorates due to serial handling

Engineering Contradiction:
Improvedata stream format compatibilityVSAvoidprocessing throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

Data streams undergo preliminary classification and formatting operations before entering the parallel processing stage. This pre-processing organizes heterogeneous streams into homogeneous groups that can be efficiently handled by specific PEs, maintaining format flexibility while preparing data for high-speed parallel processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A control mechanism acts as an intermediary between heterogeneous data inputs and parallel processing elements. This mediator translates diverse data formats into standardized intermediate representations that PEs can process in parallel, then reassembles results into the required output formats, thereby maintaining versatility while enabling efficient parallel throughput

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3739839B1Vector processor for heterogeneous data streams
Publication Date: 2025.06.25 INTEL CORP
  • EP3739839B1 patent drawingFigure 1~2
  • EP3739839B1 patent drawingFigure 3~4
  • EP3739839B1 patent drawingFigure 5~6

AI summary

A vector processor includes a grouping memory functional unit coupled to grouping memory having multiple bins. The vector processor also includes a bitformatting functional unit that performs bit-level data arrangements using any suitable technique or network, such as a Benes network. The vector processor receives and reads an input vector of data that includes portions (e.g., bits) of multiple data streams, and writes each portion corresponding to a respective data stream to a respective bin in parallel using the bitformatting functional unit to align the data. The vector processor also or alternatively receives and reads multiple outgoing data streams, writes portions of the data streams in respective bins of the grouping memory, and intersperses the portions in an outgoing vector of data in parallel, using the bitformatting functional unit to align the data.