Vector Instruction Queue Decoupling for AI Processor Layout
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Solution Overview
Problem
The high parallelism in AI processors causes challenges in chip layout and wiring, necessitating a high-performance vector processing architecture to reduce design and verification complexity.
Innovation Solution
A method and apparatus that decouple vector processing from scalar processing by generating a vector instruction queue after scalar instruction completion, performing instruction decoding, broadcasting control signals, and detecting instruction execution readiness before issuing to the vector processing unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high parallelism is used in AI processor to match high computing power, then processing capability is improved, but chip layout and wiring complexity increases
Solution Approach 1:
The processor is divided into two independent parts: a scalar processing unit and a vector processing unit. The scalar unit handles control flow and scalar operations, while the vector unit handles parallel data processing. This segmentation allows the vector unit to achieve high parallelism without increasing the overall chip complexity, as each unit has dedicated resources and clear functional boundaries.
Solution Approach 2:
A vector instruction queue is introduced as an intermediary buffer between the scalar instruction stream and the vector processing unit. The queue decouples the instruction fetch/decode pipeline from the vector execution pipeline, allowing the vector unit to process multiple data elements in parallel while the scalar unit maintains control flow. This intermediary structure enables high productivity without requiring complex interconnections.
2Ease of operation
If vector processing and scalar processing are coupled, then instruction execution is simplified, but design and verification complexity increases
Solution Approach 1:
The processing architecture is segmented into independent scalar and vector processing units with distinct instruction queues and control logic. The scalar unit executes scalar instructions sequentially, while the vector unit executes vector instructions in parallel. This segmentation simplifies verification by allowing each unit to be tested independently, reducing overall design complexity despite maintaining operational simplicity.
Solution Approach 2:
The vector instruction queue acts as a mediator that translates scalar instruction semantics into vector execution operations. It manages the conversion of scalar control flow into parallel vector operations without requiring complex inter-unit communication, thereby maintaining ease of operation while reducing design and verification complexity through clear interface boundaries.
Data Source
AI summary
Embodiments of this application provide a data processing method and apparatus to implement decoupling of vector processing and scalar processing. The data processing method includes generating a vector instruction queue according to a plurality of vector instructions in an instruction bundle after execution of a scalar instruction in the instruction bundle is completed; decoding a first instruction in the vector instruction queue to obtain a control signal set and an instruction code of the first instruction, the first instruction being a vector instruction in the vector instruction queue; broadcasting the control signal set to a vector processing unit, and detecting the first instruction according to the instruction code to obtain a detection result; issuing the first instruction to the vector processing unit when the detection result indicates that the first instruction is allowed to be issued; and executing the first instruction according to the control signal set.