Vector Reduction Circuit for Parallel Low-Cycle Computation
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Solution Overview
Problem
Existing methods for performing vector reductions, such as in neural network training and multimedia processing, are inefficient and require significant processing cycles in general processors, leading to delays and inefficiencies.
Innovation Solution
A special-purpose hardware circuit designed to perform vector reductions, capable of executing these operations in fewer cycles than general processors, without the need for off-chip computation, and optimized for efficient parallel processing of staggered data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector reductions are performed using general processors, then flexibility and programmability are maintained, but processing time and cycle counts increase significantly
Solution Approach 1:
The vector reduction operation is divided into multiple segments processed in parallel by multiple cells. Each cell handles a portion of the input vector simultaneously, reducing the overall processing time. The segmentation allows the circuit to process N elements in log2(N) cycles instead of N cycles sequentially.
Solution Approach 2:
The patent transforms the sequential one-dimensional processing into a two-dimensional hierarchical structure with multiple levels of reduction. First, elements are reduced within segments to produce intermediate results, then these intermediate results are reduced across segments. This dimensional transformation enables parallel processing and significantly reduces cycle counts.
2Productivity
If vector reductions require off-chip computations, then general-purpose processing is maintained, but processing delays and efficiency are reduced
Solution Approach 1:
Multiple reduction operations are merged into a single integrated hardware circuit that performs both intra-segment and inter-segment reductions. The circuit combines segment reduction units and inter-segment reduction logic into one cohesive structure, eliminating the need for separate off-chip computation steps and data transfers.
Solution Approach 2:
The vector reduction circuit is self-contained and performs all reduction operations internally without requiring external processing. Each cell within the circuit has the capability to perform reduction operations on its input elements and pass results to subsequent cells, making the entire reduction process self-sufficient and eliminating off-chip computation dependencies.
Data Source
AI summary
A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.