Vector Register Complex Data Continuous Access

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Solution Overview

Problem

Existing information processing systems face inefficiencies in performing complex vector operations due to the need for stride access when loading and storing real and imaginary parts of complex data, leading to slower processing speeds and the inability to execute division operations as vector operations.

Innovation Solution

The system generates instructions for continuous access and masked vector operations, allowing real and imaginary parts to be loaded and processed as elements of a vector register, enabling operations on different element numbers and accelerating memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If real-part data and imaginary-part data are loaded into different vector registers using stride access, then complex number multiplication and division can be performed, but processing speed becomes slower

Engineering Contradiction:
Improvecapability to perform complex number operationsVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent merges real-part data and imaginary-part data into the same vector register by loading them contiguously from alternately arranged memory locations. This combining approach eliminates the need for separate vector registers, enabling continuous access to memory and significantly improving processing speed while maintaining the capability to perform complex number operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Instead of the conventional approach of separating real and imaginary parts into different registers, the patent inverts this approach by interleaving them within the same register. The load instruction generates alternating real-imaginary element sequences, and subsequent mask operations selectively process the required components, thereby achieving both speed and operational versatility.

Inventive Principle:
Principle #13The other way round (Inversion)

2Ease of operation

If stride access is used to load real and imaginary parts alternately from memory, then data can be loaded into vector registers, but memory access speed decreases

Engineering Contradiction:
Improvedata loading capabilityVSAvoidmemory access speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The patent performs preliminary arrangement of real and imaginary parts in alternating sequence within the vector register during the load operation. This preliminary interleaving allows subsequent operations to directly access the required data elements without additional memory access, thereby improving memory access speed while maintaining ease of operation for complex number computations.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If specialized complex multiplication instructions are used, then multiplication can be performed efficiently, but other vector operations like division cannot be executed

Engineering Contradiction:
Improvemultiplication execution efficiencyVSAvoidsupport for multiple complex operations
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal vector operation framework that can handle addition, subtraction, multiplication, and division of complex numbers using the same basic mechanism. By loading real and imaginary parts alternately into the same vector register and using mask operations to selectively process elements, the system achieves multi-functionality without requiring specialized instructions for each operation type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12124848B2Information processing apparatus, information processing method, and program
Publication Date: 2024.10.22 NEC CORP
  • US12124848B2 patent drawing
  • US12124848B2 patent drawing
  • US12124848B2 patent drawing

AI summary

An information processing apparatus according to the present invention includes: a load instruction generating unit configured to generate an instruction to continuously access a memory in which a real part and an imaginary part composing complex data are alternately arranged, in accordance with arrangement of the real part and the imaginary part, and load the real part and the imaginary part as respective elements of a vector register; and an operation instruction generating unit configured to generate a vector operation instruction including an instruction to perform a vector operation of elements corresponding to element numbers different from each other between two vector registers and an instruction to perform a masked vector operation.