Vector Register File Selective Address Coupling

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Solution Overview

Problem

Existing vector register file (VRF) implementations suffer from reduced power efficiency due to the need to access and power elements not required for read or write operations, or by using multiple read/write ports, which increases power consumption and component costs.

Innovation Solution

A VRF design with a single read or write port, where each element bank is selectively coupled to address lines via multiplexors, allowing only the necessary elements to be accessed using a selection pattern, thereby reducing unnecessary power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple read ports or write ports are used to access different rows simultaneously, then access speed is improved, but power consumption and component cost increase

Engineering Contradiction:
Improveaccess speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic row selection by selectively coupling address lines to different element banks based on the specific access pattern required. Instead of statically connecting all rows to all ports, the system dynamically activates only the necessary row-port connections, allowing multiple ports to access different rows when needed while reducing power consumption when fewer accesses are required.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Each read port and write port is designed to be universally accessible to multiple element banks through selective coupling. A single port can serve multiple rows by dynamically connecting to different element banks, eliminating the need for dedicated ports for each row while maintaining the capability for simultaneous multi-row access when performance demands it.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If all elements in a row are accessed during read or write operations, then data integrity is ensured, but power efficiency decreases due to unnecessary element access

Engineering Contradiction:
Improvedata integrityVSAvoidpower efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by enabling different access patterns for different portions of the vector register file. Instead of uniformly accessing entire rows, the selective coupling mechanism allows precise targeting of specific element banks and columns that contain the required data, accessing only the local region needed for the operation while leaving other regions inactive to conserve power.

Inventive Principle:
Principle #3Local quality

3Device complexity

If a single read port or write port is used to access multiple elements, then component cost is reduced, but access capability is limited

Engineering Contradiction:
Improvecomponent costVSAvoidaccess capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent adds the dimension of time-dynamic connectivity to the traditional static port-element bank mapping. By introducing temporal multiplexing where address lines are selectively coupled to different element banks at different times, a single port achieves access capability equivalent to multiple ports while reducing component count. The system transitions from a two-dimensional static mapping to a three-dimensional dynamic mapping that includes the time dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9268571B2Selective coupling of an address line to an element bank of a vector register file
Publication Date: 2016.02.23 QUALCOMM INC
  • US9268571B2 patent drawing
  • US9268571B2 patent drawing
  • US9268571B2 patent drawing

AI summary

A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.