Vector Register File Access for Single-Cycle Multi-Segment Memory Loads
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Solution Overview
Problem
Existing processors face inefficiencies in performing multi-vector access to memory, particularly in loading and storing multiple vectors between the memory and the vector register file.
Innovation Solution
The processor incorporates a load-store device that enables multi-segment access to memory, allowing simultaneous reading and writing of multiple data elements across different vector registers within a single cycle, utilizing a load-store device with register pipelines of varying stages and rotation operations to optimize data placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-vector access methods are used, then the memory access structure is simple, but the processing speed and productivity are limited
Solution Approach 1:
The memory access operation is segmented into multiple independent channels, each capable of accessing different memory segments simultaneously. The load-store device is divided into multiple pipelines (first pipeline, second pipeline, third pipeline) that operate in parallel, allowing simultaneous multi-vector loading and storing operations across different memory segments without increasing overall system complexity
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling simultaneous operations across multiple memory segments and vector registers. The load-store device performs loading operations on source segments and storing operations on target segments concurrently, adding a temporal and spatial dimension to the traditional sequential access model
2Loss of time
If sequential vector loading is used, then the device structure is simple, but the time required for multi-vector access is long
Solution Approach 1:
The load-store device performs preliminary loading of data elements into the register pipelines before the actual vector operations are needed. Multiple data elements are pre-loaded from memory segments into the pipelines in advance, so that when the vector operations execute, the data is already ready, eliminating waiting time and reducing overall loading time
Solution Approach 2:
The register pipelines are designed to continuously transfer data elements from source segments to vector registers without interruption. The pipelines maintain continuous useful action by overlapping the loading of different data elements across multiple cycles, ensuring that no time is wasted on idle waiting periods during the vector loading process
3Productivity
If traditional memory access methods are used, then the access pattern is simple, but the processing throughput is limited
Solution Approach 1:
The patent merges multiple independent load and store operations into a single integrated load-store device that handles both operations simultaneously. The first pipeline handles loading from source segments while the second and third pipelines handle storing to target segments, combining multiple operations into one unified structure that increases throughput without proportionally increasing complexity
Data Source
AI summary
A processor and an operation method thereof may access a memory in multiple segments. The processor includes a vector register file (VRF) and a load-store device. When the load-store device performs a multi-segment load on the memory, the load-store device reads a plurality of data elements from a source segment of the memory, and then writes the data elements in the VRF within a single write cycle, so that the data elements are written in a same location in different vector registers of the VRF. When the load-store device performs a multi-segment store on the memory, the load-store device reads a plurality of data elements from the VRF within a single read cycle (the data elements are data elements of a same location in different vector registers), and then writes the data elements in a target segment of the memory.