Vector Register Irregular Shifting for Sample Rate Conversion
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Solution Overview
Problem
Existing sample rate conversion methods in digital signal processors require complex hardware and significant programming effort due to the need for data permutation, which increases hardware complexity and slows down the conversion process.
Innovation Solution
A method and processor architecture that perform sample rate conversion using an irregular shifting pattern in vector registers, eliminating the need for permutation by allowing data elements to be shifted according to a specified pattern and loaded from immediate or shadow registers, simplifying hardware requirements and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data permutation is used for sample rate conversion, then the conversion can be performed, but hardware complexity increases due to dedicated multiplexers and complex wiring
Solution Approach 1:
The vector register file is designed to perform both regular sequential access and irregular permutation access using the same hardware structure. By controlling the read port address generation logic, the same register file can serve as both a simple storage element and a permutation device, eliminating the need for dedicated multiplexer hardware.
Solution Approach 2:
The patent introduces an address generation unit that acts as an intermediary between the control logic and the vector register file. This unit translates software-controlled permutation patterns into physical register addresses, allowing complex data reordering to be achieved through address mapping rather than physical multiplexer wiring.
2Adaptability or versatility
If data permutation is implemented, then sample rate conversion is achieved, but an additional pipeline stage is required which slows down the conversion process
Solution Approach 1:
The patent merges the data permutation operation with the existing data loading operation. Instead of first loading data into registers and then permuting them in a separate pipeline stage, the permutation is accomplished during the load phase by generating appropriate read addresses from the vector register file, thereby combining two operations into one and eliminating pipeline delays.
3Manufacturing precision
If permutation is reconfigured for each output sample, then accurate sample rate conversion is achieved, but memory operations and vector registers are consumed increasing programming effort and DSP cycles
Solution Approach 1:
The patent pre-loads the entire set of input data elements into the vector register file before processing begins. This preliminary action allows all subsequent permutation operations to be performed by simply changing read addresses rather than performing actual data movements, eliminating the need for repeated memory operations and reducing DSP cycle consumption.
Data Source
AI summary
A system and method for performing sample rate conversion by an execution unit, including receiving an instruction, where the instruction comprises an irregular shifting pattern of data elements stored in a vector register, and shifting the data elements in the vector register according to the irregular shifting pattern. In case of upsampling the irregular shifting pattern includes an indication stating whether a memory element loads a data element from an immediate next memory element or from a second next memory element. In case of downsampling the irregular shifting pattern includes an indication stating whether a memory element in the input vector register loads a data element from an immediate next memory element, or whether the memory element loads a data element previously stored in a shadow vector register and the data element stored in the immediate next memory element is loaded into the shadow vector register.