Vector Reservation Station Scheduling for Conflict-Aware Writeback
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Solution Overview
Problem
Existing reservation stations in vector execution units experience write conflicts due to varying instruction execution times and limited register write ports, leading to inefficient resource consumption.
Innovation Solution
A reservation station design method that includes multiple instruction slots, bypass paths, and hold signals to manage instruction execution and resource allocation, determining ready operands and selecting appropriate slots based on execution ticks to avoid conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a traditional reservation station transmits one instruction per tick with a single register write port, then the device complexity is reduced, but write conflicts occur when multiple instructions complete simultaneously, reducing productivity
Solution Approach 1:
The patent segments the register file into multiple banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3) with each bank having its own write port. This segmentation allows multiple instructions to be written back simultaneously to different banks, eliminating write conflicts while maintaining a relatively simple reservation station structure. The register address is divided into bank select bits and offset bits to route writes to appropriate banks.
Solution Approach 2:
The patent introduces a new dimension to the register file architecture by organizing it as a multi-bank structure rather than a single linear file. This dimensional change from one-dimensional (single file) to two-dimensional (multiple banks with selective access) allows parallel write operations without increasing the overall footprint proportionally, thus improving throughput without excessive complexity.
2Object-affected harmful factors
If instructions are stored externally when write ports are occupied, then write conflicts are avoided, but extra register resources are consumed, increasing device complexity
Solution Approach 1:
By segmenting the register file into multiple banks with simultaneous write capability, the patent eliminates the need to store instructions externally. Multiple instructions that would have conflicted for a single write port can now be written to different banks in the same tick, avoiding both write conflicts and the need for external storage of register values.
Solution Approach 2:
The multi-bank register file enables continuous write operations without interruption. Instead of pausing to store instructions externally and wait for the write port to free up, the system maintains continuous useful action by allowing parallel writes to multiple banks, thus eliminating idle cycles and external storage dependencies.
3Productivity
If multiple register write ports are provided, then write conflicts are reduced, but the device complexity and resource consumption increase
Solution Approach 1:
The register file is segmented into multiple banks, each with its own write port. This segmentation provides multiple write capabilities while organizing the structure efficiently. The bank selection logic adds minimal complexity compared to a fully parallel multi-port register file, as writes are routed to specific banks based on address bits rather than requiring complex arbitration logic.
Solution Approach 2:
The system dynamically selects which bank receives the write operation based on the destination address. This dynamic routing allows the register file to adapt to different write patterns, providing multiple write ports when needed while maintaining a compact structure. The bank selection is performed automatically through address decoding rather than requiring dynamic reconfiguration.
Data Source
AI summary
A reservation station design method for vector execution units includes: S1, receiving an instruction by a reservation station, decoding the number of ticks for executing the instruction, and extracting an address of each source operand; S2, determining whether each source operand is ready; selecting a specific instruction slot to store the instruction, monitoring a bypass path, and pulling up a status bit of each not-ready source operand; S3, sorting non-transmitted instructions, determining a specific instruction according to a sorting result, and transmitting the specific instruction to a vector execution unit, and sending out a prewrite-back signal; and S4, setting hold signals, and blocking an instruction to be blocked; and when the address of each source operand corresponding to any one non-transmitted instruction is identical with an address in the prewrite-back signal, counting ticks, and in the last tick, transmitting a corresponding non-transmitted instruction to the vector execution unit for execution.