Vector Processing Scheduler Circuit for Operator Readiness
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Solution Overview
Problem
Vector processing in existing systems is inefficient due to sequential execution of operators, which fails to leverage parallelism and results in impractical storage requirements for intermediate results, as executing operators sequentially and storing full vectors as intermediates is neither efficient nor practical.
Innovation Solution
A scheduler circuit that determines operator readiness by comparing target and actual positions of operands, updates readiness states using state machines, and allocates operators to hardware resources based on readiness and availability, supporting both preemptive and non-preemptive allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operators are executed in strict sequential fashion, then execution simplicity is maintained, but parallelism is lost and execution efficiency deteriorates
Solution Approach 1:
The system performs preliminary actions by pre-calculating and storing target positions for all operands before execution begins. The scheduler circuit is pre-configured with operand position information, allowing it to quickly determine operator readiness without complex runtime analysis. This preliminary preparation enables efficient parallel execution while keeping the runtime scheduler relatively simple.
Solution Approach 2:
Each operator automatically determines its own readiness state by having the scheduler circuit compare its input operand positions against target positions. The system serves itself by having operators independently signal when they are ready for execution based on their input availability, eliminating the need for complex centralized control logic.
2Reliability
If full vectors are stored as intermediate results between operators, then data availability for downstream operators is ensured, but storage requirements become impractical
Solution Approach 1:
The system segments vectors into smaller chunks or blocks that are processed incrementally. Instead of storing complete vectors as intermediates, the scheduler processes and passes forward only the necessary portions of data. This segmentation allows downstream operators to receive data in manageable chunks, reducing peak storage requirements while maintaining data availability through staged processing.
Solution Approach 2:
The system performs partial action by processing and transmitting only the necessary portions of intermediate results rather than complete vectors. Downstream operators receive exactly the data they need when they need it, without requiring storage of entire vectors. This partial processing approach reduces storage consumption while ensuring data availability for subsequent operations.
3Productivity
If downstream operators wait for complete upstream operator execution, then data correctness is ensured, but parallelism and execution speed are reduced
Solution Approach 1:
The system performs preliminary action by pre-calculating target positions for all operands and making this information available to the scheduler before execution begins. This allows the scheduler to determine exactly when each operator's inputs will be ready, enabling downstream operators to start processing as soon as their specific data requirements are met, rather than waiting for complete upstream execution. Data correctness is maintained because the scheduler ensures operators only execute when their input data is actually available.
Data Source
AI summary
An apparatus includes a processor and an operator readiness circuit. The processor may be configured to schedule one or more operators used to process a plurality of vectors based on one or more status signals indicating a readiness state of the one or more operators. The operator readiness circuit may be configured to (i) compare a target position and an actual position of each operand associated with the one or more operators to determine a readiness state of each operand, (ii) update the readiness state of the operands using a plurality of state machines, and (iii) generate the one or more status signals indicating the readiness state of the one or more operators based on the readiness state of each operand associated with the one or more operators.