Pipelined Vector Signaling FEC for Low-Latency Error Correction
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Solution Overview
Problem
High-speed communications systems face challenges in minimizing error correction latency and power consumption while maintaining low Bit Error Rates (BER) in chip-to-chip communication links, particularly with vector signaling codes where existing Forward Error Correction (FEC) techniques introduce significant latency and computational power consumption.
Innovation Solution
The implementation of pipelined Forward Error Correction (FEC) processing using a vector signaling code that operates in the Galois field GF(2n), where error correction syndrome values are incrementally updated as data bits are received, allowing for concurrent error correction during data transmission and reception, reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Forward Error Correction (FEC) techniques are used for error correction in high-speed communications, then error correction capability is improved, but latency and power consumption increase significantly
Solution Approach 1:
The patent segments the error correction process into incremental updates that occur continuously as data bits are received, rather than waiting for complete codewords. The syndrome values are updated in stages, allowing error correction to begin before all data is received, thus reducing overall latency while maintaining correction capability.
Solution Approach 2:
The patent performs preliminary error correction actions by calculating syndrome values incrementally as data arrives. This allows the system to prepare error correction information in advance and begin correction processes before the complete data set is received, reducing the time needed for error correction.
2Reliability
If conventional Forward Error Correction (FEC) techniques are used for error correction in high-speed communications, then error correction capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent divides the error correction computation into segmented incremental updates that process data in smaller chunks as it arrives. This segmentation allows the system to perform computations more efficiently with lower peak power consumption, as opposed to processing all data at once which would require higher power.
Solution Approach 2:
The patent implements continuous error correction processing that operates throughout the data reception process rather than performing a single batch processing operation. This continuous operation allows for better power management and reduces overall power consumption by distributing computational load over time.
3Productivity
If pipelined FEC processing is implemented to reduce latency, then processing speed is improved, but system complexity increases
Solution Approach 1:
The patent segments the pipelined processing into distinct stages that operate on different portions of the data stream simultaneously. Each stage performs a specific function (receiving data, updating syndromes, correcting errors) which simplifies the design of individual stages while achieving high overall processing speed through parallel operation.
Solution Approach 2:
The patent implements a dynamic pipelined architecture where processing stages are activated and deactivated based on data availability. This dynamic approach allows the system to maintain high processing speed when data is available while reducing complexity by idleing stages when data is being received or processed.
Data Source
AI summary
Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.