Vector Slot Processor Micro Execution Slots for High-Speed Streaming

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Solution Overview

Problem

Current digital communication systems face challenges in efficiently processing high-speed streaming inputs for multiple demodulation standards, particularly in software defined radio platforms, due to inflexible and non-scalable designs that struggle with varying sample and symbol rates, especially in MIMO communication systems.

Innovation Solution

A vector slot processor is designed with multiple Micro Execution Slots (MES) that perform signal processing operations, featuring n-way signal and coefficient registers, Multiply and Accumulate (MAC) units, extended precision accumulators, and scalable architecture to handle filtering, down-sampling, up-sampling, and waveform interpolation operations, enabling flexible and scalable processing of high-speed inputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If application specific hardwired architectures are used, then processing speed is improved, but adaptability to multiple demodulation standards deteriorates

Engineering Contradiction:

Improveprocessing speedVSAvoidadaptability to multiple demodulation standards

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The processor is divided into multiple Micro Execution Slots (MES) that can be independently configured. Each MES contains separate signal registers, coefficient registers, and MAC units that can be programmed to perform different signal processing operations, enabling the system to be segmented into functional units that can be reconfigured for different demodulation standards while maintaining high processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The architecture employs dynamic reconfiguration capabilities where the number and configuration of MES can be adjusted at runtime. The signal registers and coefficient registers can be dynamically allocated and reconfigured to handle varying sample rates and symbol rates, allowing the system to adapt to multiple demodulation standards without sacrificing processing performance.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If DSP CPUs are used, then adaptability to multiple demodulation standards is improved, but processing speed and efficiency deteriorate

Engineering Contradiction:

Improvesupport for multiple demodulation standardsVSAvoidprocessing efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces general-purpose software-based DSP CPU operations with dedicated hardware MAC units that perform multiply-accumulate operations in parallel. This substitution of mechanical/software processing with specialized hardware acceleration maintains adaptability through programmable configuration while dramatically improving processing efficiency and throughput for high-speed streaming inputs.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The Micro Execution Slots are designed as universal processing units that can perform multiple signal processing operations including FIR filtering, decimation, interpolation, and correlation functions. Each MES contains configurable signal registers, coefficient registers, and MAC units that can be programmed to execute different algorithms, providing multi-functionality that matches the versatility of DSP CPUs while achieving hardware-level processing speed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If current FIR filter designs are used, then filtering operation is achieved, but scalability to higher sampling rates and multiple input streams deteriorates

Engineering Contradiction:

Improvefiltering operationVSAvoidscalability to higher sampling rates and MIMO systems

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent extends traditional FIR filter designs by adding a temporal dimension through pipelined Micro Execution Slots. Multiple MES operate in parallel pipelines, each handling different stages of the filtering process or different input streams. This dimensional extension allows the system to scale to higher sampling rates by distributing filter operations across multiple time-synchronized processing slots while maintaining filtering reliability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9092227B2Vector slot processor execution unit for high speed streaming inputs

Publication Date: 2015.07.28 TEJAS NETWORKS LTD

AI summary

A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.