Vector Lane Sorting With Streaming Engine Cache Bypass
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Solution Overview
Problem
Digital signal processors face challenges in efficiently managing memory bandwidth and scheduling for real-time data processing, particularly in applications requiring predictable but non-sequential input data patterns, which can lead to performance issues if transformed data is not output on schedule.
Innovation Solution
The implementation of a streaming engine within the DSP processor that includes address generation, data formatting, and storage for formatted data, capable of handling multiple data streams with six levels of nested iteration, along with instruction support for vector sorting, to improve memory access and data scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is processed through the L1D cache for vector sorting, then cache coherence is maintained, but memory bandwidth is reduced and cache miss stalls increase
Solution Approach 1:
The patent segments the data processing path into two separate pathways: a cache-coherent path through L1D for maintaining data consistency, and a high-performance path bypassing L1D for time-critical vector sorting operations. This segmentation allows simultaneous operation of both paths, achieving high throughput while maintaining cache coherence when needed.
Solution Approach 2:
The patent introduces an intermediary mechanism (copy-back logic and validation logic) that mediates between the high-speed sorting path and the cache system. This intermediary allows data to be sorted quickly in a separate buffer and then selectively copied back to L1D only when cache coherence is required, minimizing the impact on memory bandwidth and eliminating cache miss stalls for sorting operations.
2Reliability
If vector sorting is implemented with full cache coherence, then data consistency is maintained, but processing speed decreases
Solution Approach 1:
The patent implements dynamic cache coherence management where the coherence protocol is activated only when necessary. The validation logic determines whether cache coherence is required for each sorting operation, and the copy-back logic dynamically transfers data to L1D only when the sorted result needs to be visible to other cache lines. This dynamic approach maintains data consistency when needed while maximizing sorting speed when coherence constraints are not required.
3Productivity
If traditional sorting algorithms are used, then implementation simplicity is maintained, but instruction complexity increases for bitonic sorting
Solution Approach 1:
The patent performs preliminary actions by pre-configuring the bitonic sorting network structure and pre-generating the necessary control signals for each sorting stage. The comparator logic is pre-arranged in a bitonic pattern, and the control logic pre-calculates the required swap operations based on the input data characteristics. This preliminary preparation reduces the runtime complexity of the sorting operation, allowing high throughput to be achieved despite the inherent complexity of bitonic sorting algorithms.
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.