Vector Permutation Sorting for DSP Memory Bandwidth Bottlenecks

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in handling predictable but non-sequential input data patterns required for video encoding and other applications.

Innovation Solution

The implementation of a streaming engine within the DSP processor that manages data streams using six-dimensional nested loops and supports vector sorting instructions, enhancing memory access and data scheduling through autonomous address generation and formatting, thereby improving memory bandwidth and reducing cache miss stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional memory access methods are used in DSP processors, then the processor can handle basic data processing, but memory bandwidth is limited and cache miss stalls increase

Engineering Contradiction:

Improvedata processing efficiencyVSAvoidcache miss stalls

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The streaming engine performs preliminary actions by autonomously generating addresses and formatting data before the main processing units need it. The six-dimensional nested loops pre-calculate memory addresses and prepare data in the optimal order, eliminating the need for processors to wait for memory access during execution.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The streaming engine acts as an intermediary between memory and processing units. It receives data from memory, performs address generation and formatting operations, and delivers processed data to functional units, thereby decoupling the memory access timing from processing timing and reducing cache miss stalls.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If data is accessed in non-sequential patterns for video encoding, then flexible data processing is achieved, but memory bandwidth utilization decreases

Engineering Contradiction:

Improvedata access flexibilityVSAvoidmemory bandwidth utilization

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The address generation unit dynamically calculates memory addresses based on six-dimensional loop indices and data dependencies. Instead of fixed sequential access patterns, the system adapts address generation to the specific access patterns required by video encoding algorithms, maintaining both flexibility and efficiency.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent introduces six-dimensional nested loops to manage data access, adding multiple dimensions of control beyond traditional sequential access. This multi-dimensional approach enables complex non-sequential access patterns (such as those required for video encoding) while maintaining efficient memory bandwidth utilization through coordinated loop unrolling and address pre-calculation.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11829300B2Method and apparatus for vector sorting using vector permutation logic

Publication Date: 2023.11.28 TEXAS INSTRUMENTS INC

AI summary

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.