Vector Suffix Comparisons for Boyer-Moore String Search
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Solution Overview
Problem
Current string search algorithms, such as the Boyer-Moore algorithm, are computationally intensive and require numerous processing cycles due to the need for scalar comparators, limiting their efficiency and increasing power consumption and processing time, especially for complex operations like text string searches.
Innovation Solution
The implementation of extended vector suffix comparisons using SIMD instructions allows for simultaneous comparison of multiple data units, enabling larger shifts of the sliding window and reducing the number of required shifts, thereby enhancing processing speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If scalar comparators are used for string search operations, then the algorithm can be implemented with simple hardware, but the processing time and number of processing cycles increase significantly
Solution Approach 1:
The patent merges multiple scalar comparison operations into a single vector comparison operation using SIMD instructions. Instead of comparing one character at a time with separate scalar comparators, the invention loads multiple characters into vector registers and performs parallel comparisons, combining the functionality of multiple scalar units into one vector unit that processes multiple data elements simultaneously.
Solution Approach 2:
The patent replaces the mechanical sequential execution of scalar comparison operations with a vectorized parallel processing system. By using SIMD (Single Instruction Multiple Data) instructions, the invention substitutes the traditional scalar processing mechanism with a vector processing mechanism that can compare multiple character pairs in a single clock cycle, dramatically reducing processing time.
2Measurement precision
If multiple processing cycles are required for each comparison operation, then processing precision can be maintained, but power consumption increases
Solution Approach 1:
The patent enables continuous parallel comparison operations by keeping vector registers filled with data and performing comparisons without returning to scalar operations. The vector comparison instructions process multiple character pairs continuously in parallel, maintaining high utilization of the comparison logic and reducing the total number of processing cycles required to complete a string search, thereby reducing power consumption.
3Ease of manufacture
If scalar comparisons are performed sequentially, then implementation is straightforward, but throughput is limited
Solution Approach 1:
The patent transitions from one-dimensional sequential scalar processing to multi-dimensional parallel vector processing. By organizing character data into vector registers with multiple lanes and performing comparisons across all lanes simultaneously, the invention adds a dimension of parallelism to the comparison operation, dramatically increasing throughput while maintaining relative implementation simplicity through standardized SIMD instruction sets.
4Reliability
If the sliding window shifts one position at a time, then no match is missed, but the number of shifts and processing cycles increases
Solution Approach 1:
The patent performs preliminary vector comparisons that can identify multiple potential match positions simultaneously. By comparing multiple characters ahead of the current window position in parallel, the vectorized approach can determine that no match exists for several upcoming positions, allowing the algorithm to skip ahead rather than shifting one position at a time, thus maintaining reliability while increasing search speed.
Data Source
AI summary
Instructions and logic provide extended vector suffix comparisons for Boyer-Moore searches. Some embodiments, responsive to an instruction specifying: a pattern source operand and a target source operand, compare each of m data elements of the pattern operand with each data element of the target operand. A first and second equal ordered aggregation operation are performed from the comparisons according to the m data elements of the pattern source operand. A result of the first and second aggregation operations indicating whether or not a possible match exists between the m data elements of the pattern source operand and d data element positions relative to data elements of the target source operand is stored. Ordering of the data elements of the pattern and the target operands may be reversed for the second aggregation operation, and d may be a sum of m−1 and the quantity of target operand elements in some embodiments.


