Vector-Switched Error Detection Circuit for Lower Layout Load
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Solution Overview
Problem
Conventional error detection circuits require significant circuit area and signal processing load due to the need to accommodate all data bits for error detection, leading to increased layout complexity and reduced margin for global line wiring in data processing apparatuses.
Innovation Solution
An error detection circuit that includes an error operation unit, a vector storage unit, and a vector switching unit, which outputs error detection codes in response to control signals and vectors, reducing the need to process all data bits simultaneously by shifting and sharing operation units across unit intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a logic circuit performs error detection operation on all data bits of input/output units, then error detection capability is improved, but circuit area and signal processing load increase
Solution Approach 1:
The patent segments the error detection process into multiple unit intervals, where each interval processes a subset of data bits. The 72 data bits are divided into groups that are processed sequentially across different unit intervals, allowing the logic circuit to handle fewer bits at each stage rather than all bits simultaneously, thereby reducing circuit area and processing load while maintaining comprehensive error detection coverage.
Solution Approach 2:
The patent implements periodic error detection operations across multiple unit intervals. The error detection logic operates in a periodic manner, processing different data bit groups in successive time intervals according to a predetermined pattern. This periodic action allows the same logic circuit to be reused across multiple intervals, reducing the need for dedicated circuits for all data bits and thereby reducing overall circuit area and processing load.
2Reliability
If global line wiring transmits all data bits to error detection circuit, then complete data transmission is achieved, but layout margin is reduced
Solution Approach 1:
The patent segments the data transmission path into multiple global line groups, where each group transmits a subset of data bits to the error detection circuit during different unit intervals. Instead of requiring all 72 data bits to be transmitted simultaneously through global lines, the data is divided and transmitted in sequences, reducing the number of global lines needed at any given time and thereby increasing layout margin while maintaining complete data transmission capability.
Data Source
AI summary
An error operation unit configured to output an error detection code in response to a plurality of control signals, a plurality of vectors and data, a vector storage unit configured to store the plurality of vectors, and a vector switching unit configured to provide the plurality of vectors to the error operation unit in response to the plurality of control signals are included.