Vectorized Sparse Convolution via SIMD Thread Segmentation
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Solution Overview
Problem
Conventional sparse convolution techniques are inefficient due to high computational expense and power consumption, particularly when implemented on graphics processing units (GPUs), and they often lack effective parallelization and vectorization, making them unsuitable for limited hardware resources like digital signal processors (DSPs).
Innovation Solution
The implementation of parallelized, vectorized, and single instruction multiple data (SIMD) operations using thread-level parallelism and scatter-accumulate techniques for sparse convolution, which identifies affected output elements, generates intermediate values, and accumulates them efficiently, allowing for reduced computational expense and power consumption while utilizing less complex hardware like DSPs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sparse convolution is implemented on GPUs with single-threaded operations, then computational operations can be performed, but parallelization is ineffective and power consumption is high
Solution Approach 1:
The patent segments the convolution computation into independent thread blocks, where each block handles a specific output element. This segmentation enables parallel execution across multiple GPU threads while reducing the computational burden on each individual thread, thereby improving overall computational efficiency and reducing power consumption through better resource utilization.
Solution Approach 2:
The patent implements sparse convolution by performing computations only on non-zero input elements rather than all elements. This partial action approach eliminates wasted computational operations on zero-valued inputs, significantly improving computational efficiency and reducing the energy required for convolution operations.
2Productivity
If conventional sparse convolution techniques are used, then convolution operations can be performed on sparse inputs, but computational expense is high due to unnecessary multiplications
Solution Approach 1:
The patent extracts and processes only the non-zero elements from the sparse input tensor, separating them from the zero-valued elements. By taking out only the relevant computational data, the system performs convolutions exclusively on necessary inputs, eliminating wasteful multiplications and reducing computational expense while maintaining convolution operation speed.
3Device complexity
If sparse convolution is performed on limited hardware like DSPs, then device complexity is reduced, but effective implementation of conventional techniques is difficult
Solution Approach 1:
The patent changes the computational parameters and data formats to be optimized for DSP architectures. By adjusting the computation stride, block size, and memory access patterns to match DSP capabilities, the implementation becomes feasible on limited hardware while maintaining acceptable performance, thus resolving the contradiction between reduced device complexity and implementation ease.
Data Source
AI summary
Certain aspects of the present disclosure provide techniques and apparatus for vectorized sparse convolution. An input tensor for a convolution operation using a convolution kernel is accessed, where the input tensor comprises a set of valid elements. An aggregated output value is generated for a valid element of the set of valid elements in the input tensor, by determining a set of one or more affected output elements based on the convolution kernel; generating, for each respective affected output element of the set of one or more affected output elements, a respective intermediate value based on the convolution kernel and the valid element; and accumulating the respective intermediate values to generate the aggregated output value. The aggregated output value is output.