vECU Error-Out Signaling for Stuck-at-Fault Detection

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Solution Overview

Problem

Virtual electronic control units (vECUs) in a system on a chip (SoC) may experience faults, requiring fault recovery to prevent disruption to other vECUs, while maintaining a known and defined state during recovery.

Innovation Solution

A fault collection and control unit (FCCU) generates an error out (EOUT) signal using toggled or static signals on EOUT pins to indicate the vECU's state, allowing detection of stuck-at-faults and enabling fault recovery without redundant pins, and managing fault recovery through local or SoC resets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a vECU experiences a fault and requires fault recovery, then the vECU can be reset to a known state, but the EOUT pin may remain stuck at a fault indication even after successful recovery

Engineering Contradiction:
Improvefault recovery reliabilityVSAvoidstuck-at-fault detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies periodic action by toggling the EOUT signal at a defined frequency during normal operation. This periodic toggling allows the external device to detect whether the EOUT pin is functioning properly. If the pin is stuck at a fault indication after recovery, the absence of toggling reveals the stuck-at-fault condition, enabling detection without requiring redundant pins.

Inventive Principle:
Principle #19Periodic action

2Difficulty of detecting and measuring

If redundant pins are added to detect stuck-at-fault conditions, then fault detection capability is improved, but the number of pins and device complexity increases

Engineering Contradiction:
Improvestuck-at-fault detection capabilityVSAvoidnumber of pins
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent makes the EOUT pin multi-functional by using it for both normal fault indication and stuck-at-fault detection. During normal operation, the EOUT pin toggles to indicate operational status. During fault recovery, the same pin's lack of toggling indicates a stuck-at-fault condition. This eliminates the need for separate redundant detection pins, reducing device complexity while maintaining detection capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of information

If the EOUT signal is continuously toggled to indicate normal state, then the state indication is clear, but power consumption increases

Engineering Contradiction:
Improvestate indication clarityVSAvoidpower consumption
Core Design Contradiction:
Loss of informationVSUse of energy by moving object

Solution Approach 1:

The patent uses periodic toggling of the EOUT signal at a defined frequency during normal operation to provide clear state indication. The periodic nature allows external devices to detect the state through frequency analysis while enabling stuck-at-fault detection. During fault conditions, the toggling stops, providing clear fault indication without continuous power consumption during actual fault states.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP4675437A1Method and apparatus for generating an error out (EOUT) signal indicating a state of a virtual electronic control unit (VECU)
Publication Date: 2026.01.07 NXP BV
  • EP4675437A1 patent drawingFigure 1
  • EP4675437A1 patent drawingFigure 2
  • EP4675437A1 patent drawingFigure 3A

AI summary

An error out (EOUT) controller of a system on a chip (SoC) for fault management generates a first EOUT signal which indicates a virtual electronic control unit (vECU) of the SoC comprising a plurality of vECU is in a first state. The first EOUT signal is output, where the first EOUT signal is toggled at a first toggle frequency. A fault signal which indicates the vECU having a fault is received. Based on receiving the fault signal, an EOUT circuit is selected from a plurality of EOUT circuits and the selected EOUT circuit generates a second EOUT signal which indicates the vECU is in a second state. The second EOUT signal is then output, where the second EOUT signal is a toggled at a second toggle frequency or is a static signal.