Vehicle Control System Synchronization Circuit

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Solution Overview

Problem

Existing vehicle control systems face challenges in maintaining synchronization between control systems when one system transitions from a stopped state to an operating state, leading to potential motor pulsation and discomfort for the driver due to timing deviations.

Innovation Solution

A vehicle control system with multiple control circuits and a monitoring circuit that synchronizes operations based on a synchronization signal generated by an operating control circuit, ensuring that when one control circuit resumes operation, its timing is aligned with the continuously operating circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the second control system determines processing timing based on its own clock pulse when the first control system is stopped, then the motor control can continue, but the processing timing may deviate when the first control system resumes operation

Engineering Contradiction:
Improvecontinuous motor controlVSAvoidsynchronization timing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a synchronization signal as an intermediary between the first and second control systems. The second control system receives and uses this synchronization signal from the first control system to align its processing timing, thereby maintaining synchronization precision while continuing motor control operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the second control system monitors the synchronization signal from the first control system and adjusts its processing timing accordingly. This feedback loop ensures that timing deviations are corrected when the first control system resumes operation, maintaining synchronization accuracy.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If the first control system transmits synchronization signal every clock pulse, then synchronization precision is maintained, but system complexity increases

Engineering Contradiction:
Improvesynchronization precisionVSAvoidcontrol system complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent employs periodic action by transmitting the synchronization signal at specific intervals rather than continuously with every clock pulse. This periodic transmission maintains synchronization precision while reducing the frequency of signal transmissions, thereby lowering system complexity and resource consumption.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If the second control system operates independently with its own clock pulse, then system autonomy is improved, but timing synchronization deteriorates

Engineering Contradiction:
Improvesystem autonomyVSAvoidtiming synchronization
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by enabling the second control system to switch between two operational modes: operating independently with its own clock pulse when the first control system is stopped, and synchronizing with the first control system's signal when it is operating. This dynamic adaptation maintains both autonomy and synchronization precision depending on system conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10266129B2Vehicle control system
Publication Date: 2019.04.23 JTEKT CORP
  • US10266129B2 patent drawing
  • US10266129B2 patent drawing
  • US10266129B2 patent drawing

AI summary

Provided is a vehicle control system that appropriately performs synchronization control for a plurality of control systems. A monitoring circuit generates a command signal when only a first reset signal is input. The monitoring circuit generates a command signal when the state in which only the first reset signal is input is changed to the state in which the input of the first reset signal is stopped. With the command signal, a second clock signal is output to a timer generator as a second timing signal. With the command signal, the second clock signal generated by a second synchronization signal generating circuit is output to a first synchronization signal generating circuit, and a third clock signal generated by the first synchronization signal generating circuit is output to a timer generator as a first timing signal.