Motor Vehicle Controller Programming with Parallel Memory Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for programming motor vehicle control units with flash modules or flash EEPROMs are inefficient due to the longer time required for writing information compared to reading, especially when complex software updates are needed, leading to prolonged workshop visits and increased costs.
Innovation Solution
The method involves utilizing a processor to perform simultaneous checks and writes across two physically separate memory areas, leveraging unused resources to accelerate the programming process by using CRC, hash value comparison, and signature methods to ensure data integrity, thereby reducing processor load and programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential writing to multiple memory chips is performed, then data integrity can be verified, but programming time increases significantly
Solution Approach 1:
The patent performs verification of the first memory area while writing to the second memory area, rather than waiting until all writing is complete. This preliminary verification action overlaps with the writing process, reducing total programming time while maintaining data integrity checks
Solution Approach 2:
The patent keeps the processor continuously utilized by performing verification operations during the writing process to the second memory area. This eliminates idle time between writing and verification, maintaining continuous useful action throughout the programming process
2Productivity
If verification is performed after writing to all memory areas, then processor load is managed, but total processing time increases
Solution Approach 1:
The patent dynamically adjusts when verification operations are performed, executing them during periods when the processor is writing to memory areas rather than after all writing is complete. This dynamic scheduling optimizes both productivity and processor load management
3Quantity of substance
If multiple memory chips are used to provide increased storage space, then memory capacity increases, but programming complexity increases
Solution Approach 1:
The patent divides the memory storage into multiple separately addressable memory areas (first memory area, second memory area) that can be written to and verified independently. This segmentation allows increased storage capacity while managing complexity through structured organization
Solution Approach 2:
The patent combines verification of the first memory area with the writing process to the second memory area, merging two operations that would traditionally be sequential into a concurrent process, thereby reducing overall programming complexity
Data Source
AI summary
The invention relates particularly to a method for programming a controller in a motor vehicle, where the controller has at least one program-controlled processor and at least two individually addresssable memory areas, particularly at least two physically separate memory chips. To speed up the writing of memory contents, the invention proposes that the processor at least intermittently perform or prompt the following steps, largely simultaneously. First, checking whether programs, program parts and/or data already written to the first memory area correspond to the data needing to be written to the first memory area, and secondly writing a program, a program part and/or data to the second memory area.