Vehicle CPU Power-Saving Release Timing for Control Deadlines
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Solution Overview
Problem
Existing automatic driving systems face challenges in ensuring timely power saving mode release to maintain control processing within time constraints, leading to potential control quality issues due to missed timing and increased power consumption.
Innovation Solution
A vehicle control device with a power saving execution determination unit that dynamically shifts between normal and power saving modes based on preset conditions, ensuring the CPU load remains within safe limits by adjusting CPU frequency, thereby preventing control processing delays and optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the CPU frequency is reduced to save power, then power consumption is reduced, but control processing may not complete within time constraints
Solution Approach 1:
The patent applies dynamic voltage and frequency scaling (DVFS) to dynamically adjust the CPU frequency based on the current operational state and power saving conditions. The control unit monitors whether power saving mode can be released and adjusts the CPU frequency accordingly, allowing the system to operate at lower frequencies when possible and higher frequencies when control processing deadlines are at risk, thus resolving the contradiction between power saving and processing reliability.
Solution Approach 2:
The patent changes the CPU frequency parameter dynamically based on power saving conditions and processing requirements. By adjusting this critical parameter, the system can optimize power consumption during normal operation while ensuring that control processing completes within time constraints when necessary, directly addressing the contradiction between energy efficiency and processing reliability.
2Reliability
If power saving mode is released too early, then control processing time constraint may be violated, but if released too late, then power consumption increases
Solution Approach 1:
The patent implements preliminary determination of power saving release timing by the control unit. Before actually releasing power saving mode, the control unit determines whether the timing is appropriate based on current system state and predicted processing requirements. This preliminary action prevents both premature release (which would violate time constraints) and delayed release (which would increase power consumption), optimizing the balance between reliability and energy efficiency.
Solution Approach 2:
The patent employs feedback mechanisms where the control unit continuously monitors system state, processing progress, and power consumption levels to determine the optimal timing for releasing power saving mode. This feedback loop ensures that power saving mode is released at the precise moment needed to satisfy time constraints while minimizing unnecessary power consumption, directly resolving the timing contradiction.
3Device complexity
If a single power saving condition is used, then the system is simple to implement, but the timing for releasing power saving mode may be missed
Solution Approach 1:
The patent segments the power saving determination into multiple independent conditions that are evaluated separately by the control unit. Rather than relying on a single condition that might be missed, the system checks multiple conditions (such as current system state, processing load, and predicted future state) to comprehensively determine the optimal release timing. This segmentation increases reliability without significantly increasing overall system complexity.
Solution Approach 2:
The patent applies partial action by evaluating multiple power saving conditions but only requiring that the necessary conditions for release are met, not all possible conditions. This approach ensures reliable timing determination without implementing excessive complexity, striking a balance between thoroughness and practical implementability.
Data Source
AI summary
Provided is a vehicle control device capable of executing control processing by utilizing a power saving execution determination unit that determines a shift to or a release from a normal mode to a power saving mode on the basis of a preset power saving condition, and a power saving execution unit that executes power saving control of the CPU by determining a shift to the power saving mode and stops the power saving control of the CPU by determining a release of the power saving mode. Then, the power saving execution determination unit has a plurality of power saving conditions, determines to shift to the power saving mode in a case where all of the plurality of power saving conditions are satisfied, and determines to release the power saving mode in the case of being changed to a state in which some of the power saving conditions are not satisfied.


