Vehicle Gateway Shared Memory for Low-Latency Inter-Processor Messaging
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Solution Overview
Problem
Existing vehicle network gateways face challenges in achieving high-speed and real-time data transmission due to low bandwidth and unnecessary memory copy, leading to latency and memory overhead during inter-processor communication.
Innovation Solution
A signal processing device with a first and second processor, each handling different communication schemes, and a shared memory for inter-processor communication, along with cache management and priority queuing to minimize latency and buffer occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional communication protocols (UART, SPI) are used for inter-processor communication, then device compatibility and ease of implementation are improved, but data transmission speed and bandwidth are limited
Solution Approach 1:
The patent changes the communication interface parameters by transitioning from traditional UART/SPI protocols to a high-speed serial communication interface with configurable baud rates and data widths, enabling adaptation between different speed requirements while maintaining protocol flexibility
Solution Approach 2:
The communication interface is designed with dynamic parameters including configurable data transmission rates, adjustable buffer sizes, and flexible protocol selection that can adapt to different communication scenarios, allowing the system to optimize between speed and compatibility based on real-time requirements
2Reliability
If multiple copies of data are stored in buffers during inter-processor communication, then data reliability and error handling are improved, but memory overhead and latency increase
Solution Approach 1:
The patent extracts the redundant data copying operation from the communication process by implementing a shared memory mechanism where data is written once and read by multiple processors, eliminating unnecessary memory copy operations while maintaining data reliability through atomic access control
Solution Approach 2:
A shared memory buffer acts as an intermediary between processors, allowing data to be transmitted directly without multiple copies in separate buffers. The shared memory includes status flags and synchronization mechanisms that ensure reliable data transfer while minimizing memory overhead
3Device complexity
If all data messages are transmitted with equal priority, then system simplicity and ease of management are improved, but real-time transmission of high-priority events cannot be ensured
Solution Approach 1:
The patent segments the communication buffer into multiple priority levels (high priority, normal priority, low priority) with separate queue structures for each level. High-priority events such as safety-critical messages are placed in dedicated queues that are serviced before lower-priority traffic, ensuring real-time transmission without significantly increasing overall system complexity
Solution Approach 2:
Different quality of service parameters are applied to different data streams based on their priority requirements. High-priority communication channels receive guaranteed bandwidth and lower latency treatment, while lower-priority channels can utilize available resources, creating localized optimization without uniform complexity across the entire system
4Reliability
If large buffers are allocated for data transmission, then data loss prevention and buffer occupancy management are improved, but memory overhead and access efficiency deteriorate
Solution Approach 1:
The patent implements circular buffers with overflow protection that allocate memory dynamically based on actual communication needs rather than maximum theoretical requirements. The buffer management includes wrap-around addressing and full/empty flag mechanisms that prevent data loss while utilizing only the necessary memory portion, avoiding waste of resources on excessive buffer allocation
Data Source
AI summary
A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.