Velocity-Based Write Disturb Refresh for Non-Volatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As non-volatile memory (NVM) technologies scale, they face challenges in maintaining a sufficient write disturb refresh rate without limiting write bandwidth due to increased thermal crosstalk and data loss in neighboring cells, especially with frequent write operations.
Innovation Solution
Implementing a velocity-based write disturb refresh method that adjusts the refresh rate based on the write-to-write delay, using a demarcation voltage to increment a write counter at higher rates for short delays and lower rates for longer delays, thereby managing thermal crosstalk effectively and optimizing bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic write operations are issued to neighboring cells at a constant rate to prevent data loss, then data retention reliability is improved, but write bandwidth is limited
Solution Approach 1:
The patent implements dynamic write disturb refresh rate adjustment based on actual write activity patterns. Instead of using a constant refresh rate, the system monitors write operations to target cells and adjusts the refresh rate of neighboring cells in real-time. When write activity is high, the refresh rate increases to prevent data loss; when write activity is low, the refresh rate decreases to allow higher write bandwidth. This dynamic adaptation resolves the contradiction between maintaining reliability and achieving high productivity.
Solution Approach 2:
The system changes the parameter of refresh rate from a fixed constant to a variable that adapts to workload conditions. By monitoring write-to-write delay and other parameters, the system adjusts the refresh rate parameter dynamically, allowing it to optimize between data retention reliability and write bandwidth based on current operational conditions.
2Productivity
If NVM technologies are scaled to improve write bandwidth, then write bandwidth is improved, but thermal crosstalk increases causing data loss
Solution Approach 1:
The patent implements a feedback mechanism that monitors write operations and their timing patterns, then uses this information to control the refresh operations of neighboring cells. The system detects write-to-write delay and other characteristics, feeds this information back to the controller, which then adjusts the refresh rate accordingly. This feedback loop allows the system to manage thermal crosstalk effectively while maintaining high write bandwidth, as the refresh operations are precisely targeted based on actual thermal disturbance patterns.
3Productivity
If write-to-write delay is short indicating high write velocity, then write bandwidth is improved, but data loss in neighboring cells increases
Solution Approach 1:
The system dynamically adjusts the refresh rate of neighboring cells based on the measured write-to-write delay. When short delays indicate high write velocity and potential thermal crosstalk, the refresh rate is increased dynamically to prevent data loss. When longer delays are observed, the refresh rate is reduced, allowing the system to maintain high write bandwidth without unnecessary refresh operations. This dynamic response resolves the contradiction between maintaining reliability under high-speed writes and achieving high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances performance by reducing data loss and increasing write disturb capability, allowing memory controllers to maintain pace with write disturb events at high write bandwidths without limiting bandwidth, resulting in up to ˜5% performance gains and improved bandwidth management.
Implementation Method 1
Writing to a non-volatile memory (NVM) cell typically results in thermal crosstalk to neighboring cells and potential data loss in the neighboring cells
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that determines a write-to-write delay with respect to a memory cell, wherein one or more neighboring cells are adjacent to the memory cell and controls a write disturb refresh rate of the one or more neighboring cells based on the write-to-write delay. In one example, the technology increments a write counter corresponding to the memory cell by a first value if the write-to-write delay exceeds a delay threshold and increments the write counter by a second value if the write-to-write delay does not exceed the delay threshold, wherein the second value is greater than the first value, and wherein the write disturb refresh rate is controlled based on the write counter.