Automated Verification Code Generation for Hardware Design
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Solution Overview
Problem
Current verification systems for memory subsystems and ASICs face challenges in ensuring accurate and efficient generation of verification code for cover groups due to complexity, typographical errors, and lack of linkage between cover groups and hardware design, leading to inadequate verification and potential latent defects.
Innovation Solution
An automated system for generating verification code based on user-input cover group attributes and hardware design, which automatically suggests cover group attributes and maintains linkages between requirements, features, sub-features, and cover groups, ensuring compliance with verification standards and reducing development cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual verification code generation is used, then flexibility and adaptability are maintained, but complexity, typographical errors, and lack of linkage between cover groups and hardware design occur
Solution Approach 1:
The system enables self-service by allowing the verification system to automatically generate verification code based on hardware design data and cover group attributes without requiring manual intervention for code generation. The system processes design data, generates verification code, and maintains linkages automatically, reducing human error while managing complexity through automation.
Solution Approach 2:
The patent replaces the mechanical manual writing process with an automated computational system. Instead of manually writing verification code, the system uses algorithms to process hardware design data and generate verification code automatically, eliminating typographical errors and improving consistency while reducing the operational complexity burden on verification engineers.
2Manufacturing precision
If automated verification code generation is implemented, then verification accuracy and consistency are improved, but system complexity increases
Solution Approach 1:
The system introduces an intermediary layer between hardware design data and verification code generation. This intermediary processing layer automatically extracts relevant information from design data, maps it to cover group attributes, and generates verification code accordingly. This intermediary mechanism manages the complexity by providing structured processing steps rather than direct complex transformations.
Solution Approach 2:
The system manages complexity by changing parameters in a controlled manner - transforming hardware design data parameters into verification code parameters through defined conversion rules. The system processes data through standardized parameter transformations that maintain precision while managing the complexity of the automation system through systematic parameter mapping.
3Reliability
If comprehensive linkage between cover groups and hardware design is maintained, then verification completeness is improved, but system complexity and data management burden increase
Solution Approach 1:
The system segments the linkage management by organizing data into distinct structured components - hardware design data, cover group attributes, and verification code - with defined relationships between them. This segmentation allows comprehensive linkages to be maintained through structured data organization rather than monolithic data management, reducing the burden while maintaining completeness.
Solution Approach 2:
The system achieves multi-functionality by having the verification system perform multiple functions - processing hardware design data, generating verification code, maintaining linkages, and ensuring completeness - all within a single integrated system. This universal approach manages the quantity of data linkages through a unified processing framework rather than separate management systems.
Data Source
AI summary
A method for performing verification and testing of a device under test (DUT) is described. The method includes receiving, by a processing device, inputs from a user regarding a hardware design for the DUT. The processing device presents cover group attribute suggestions to the user based on the hardware design and receives cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions. Based on the cover group information, the processing device automatically generates verification code, including one or more cover group definitions.