Hardware Verification Coverage Visualization for DUT White Spots
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Solution Overview
Problem
Current hardware verification tools lack the capability to create structural visualizations that easily identify 'white spots' in the design under test (DUT) and correlate these with coverage percentages, making it difficult to assess verification completeness and efficiency.
Innovation Solution
A method and device that integrates functional and code coverage analysis with structural visualization capabilities, allowing for the overlay of coverage data onto the DUT structure to identify areas requiring further testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If coverage analysis is performed using traditional verification tools, then verification completeness can be assessed, but the ability to visually identify white spots and correlate with DUT structure is insufficient
Solution Approach 1:
The patent introduces a visualization tool as an intermediary between coverage data and DUT structure. This tool receives coverage information from verification tools and presents it overlaid on the DUT schematic, enabling engineers to visually identify white spots without requiring direct analysis of raw coverage data against the hardware structure.
Solution Approach 2:
The patent transforms one-dimensional coverage metrics into two-dimensional visual representations by overlaying coverage data on the DUT schematic diagram. This dimensional change allows engineers to simultaneously view structural information and coverage status, making white spots immediately visible through visual contrast rather than requiring sequential analysis.
2Productivity
If verification metrics are analyzed separately from DUT structure, then coverage data can be processed, but the correlation between coverage percentages and DUT structure remains difficult
Solution Approach 1:
The patent merges coverage data with DUT structure by overlaying verification metrics directly onto the schematic representation. This combination allows the visualization tool to simultaneously display structural information and coverage status for the same visual element, eliminating the need to switch between separate views and preserving the correlation between coverage percentages and specific DUT components.
3Loss of time
If traditional coverage reports are provided, then verification progress can be monitored, but the ability to quickly identify areas requiring further testing is limited
Solution Approach 1:
The patent employs color coding in the visualization tool to represent different coverage states. Areas with high coverage are displayed in one color while white spots or low coverage areas are highlighted in contrasting colors. This color-change mechanism enables engineers to instantly identify testing gaps at a glance without manually analyzing coverage percentages, significantly improving ease of operation.
Data Source
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AI summary
The invention relates to a method of operating a hardware verification device (10) comprising the following steps: Receiving a verification plan (22) defining the metrics to be covered by verification simulations of the design under test (12) using the hardware description representation (18), wherein the verification plan (22) defines at least one coverage metric for describing a verification coverage related to the verification; performing verification simulations of the design under test (12) according to the verification plan (22); generating based on the respective global coverage level values (32) for the respective hardware modules (20) respective global coverage level values (32) for the respective schema modules (16) according to a predefined conversion table (36);providing the respective global coverage level values (32) for the respective schema modules (16) to the schema representation (14) of the design under test (12); Providing a signal (40) comprising the schema representation (14) of the design under test (12).