Electronic Design Verification Domain Reduction via Comparison Graph Coloring

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Solution Overview

Problem

Modern electronic designs with increased complexity and circuit components pose challenges for verification tools due to larger domain sizes, leading to performance issues in domain reduction.

Innovation Solution

A method involving data flow extraction and construction of a comparison graph with coloring to reduce the domain size of electronic designs for verification, using tokens and edges to represent signal comparisons and infer implied relations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional verification approaches compare all possible values of variables (e.g., 256 values for 8-bit variables), then verification completeness is improved, but computation time and memory usage increase significantly

Engineering Contradiction:

Improveverification completenessVSAvoidcomputation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the necessary comparison information from the electronic design by constructing a comparison graph that identifies which signal pairs are actually compared. This extraction approach removes unnecessary verification of all possible value combinations and focuses only on the specific comparisons that matter for the design, thereby reducing computation time while maintaining verification completeness.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the verification problem by dividing the electronic design into discrete comparison operations represented as edges in a comparison graph. Each edge represents a specific comparison between two signals, allowing the verification process to be broken down into manageable segments rather than treating all variable comparisons as a single exhaustive problem.

Inventive Principle:

Principle #1Segmentation

2Reliability

If conventional verification approaches compare all possible values of variables (e.g., 256 values for 8-bit variables), then verification completeness is improved, but memory consumption increases significantly

Engineering Contradiction:

Improveverification completenessVSAvoidmemory consumption

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential comparison relationships from the electronic design by building a comparison graph that represents which signals are compared. This extraction eliminates the need to store and process all possible value combinations in memory, reducing memory consumption to only the necessary comparison information.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the verification data into discrete comparison operations represented as edges in the comparison graph. This segmentation allows memory to be used efficiently by storing only the specific comparison relationships that exist in the design rather than allocating memory for all possible variable combinations.

Inventive Principle:

Principle #1Segmentation

3Productivity

If the domain size is reduced by using fewer comparison operations, then computation efficiency is improved, but verification accuracy may deteriorate

Engineering Contradiction:

Improvecomputation efficiencyVSAvoidverification accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary action by constructing the comparison graph before verification to identify all necessary comparison operations. This preliminary analysis ensures that no important comparisons are omitted while still eliminating unnecessary ones, thereby maintaining verification accuracy while improving computation efficiency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The comparison graph construction process provides feedback about which signal pairs are actually compared in the electronic design. This feedback information is used to guide the verification process, ensuring that all necessary comparisons are performed while avoiding redundant operations, thus maintaining accuracy while improving efficiency.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9928336B1Methods, systems, and articles of manufacture for simplifying an electronic design for verification by domain reduction

Publication Date: 2018.03.27 CADENCE DESIGN SYST INC

AI summary

Disclosed are techniques for simplifying an electronic design for verification by domain reduction. These techniques extract one or more data flows for at least a portion of an electronic design under verification, construct a comparison graph comprising tokens and edges for the at least the portion of the electronic design, color the comparison graph with a number of colors, and reduce a domain size of the at least the portion of the electronic design based in part or in whole upon the number of colors.