Verification Engine Composition for Resource Allocation
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Solution Overview
Problem
The increasing complexity of chip verification due to the relentless growth in transistors on a single electronic chip makes traditional simulation methods time-consuming and difficult, prompting the need for more efficient verification methods like formal verification. However, existing formal verification systems face challenges in predicting the success and resource requirements of verification engines, and integrating new engines into the verification process.
Innovation Solution
A system and method for managing and composing verification engines, allowing for user-specified computing resources and easy integration of new engines, which supports serial, parallel, and distributed compositions of verification tasks, enabling efficient allocation of resources and reporting of results through a client-server architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verification engines are run to increase verification success rate, then verification reliability is improved, but computing resource consumption increases
Solution Approach 1:
The system dynamically allocates computing resources to verification engines based on real-time performance metrics and resource availability. The resource allocation is adjusted during execution to optimize the balance between verification success rate and computing resource consumption, allowing the system to adapt to changing conditions rather than using static resource allocation.
Solution Approach 2:
The system changes operational parameters such as resource allocation weights, engine selection criteria, and execution priorities based on observed performance. By dynamically adjusting these parameters, the system can improve verification reliability while preventing excessive resource consumption, resolving the contradiction between running multiple engines and resource usage.
2Productivity
If new verification engines are integrated quickly to access state-of-the-art capabilities, then verification effectiveness is improved, but system complexity increases
Solution Approach 1:
The system employs a universal interface and standardized composition mechanisms that allow different verification engines to be integrated through common protocols. This multi-functional approach enables new engines to be added quickly without increasing system complexity, as the same integration framework handles diverse engine types and capabilities.
Solution Approach 2:
The verification system is segmented into modular components with clear interfaces. New verification engines can be integrated as independent modules without affecting the core system architecture. This segmentation allows for rapid incorporation of state-of-the-art engines while maintaining manageable system complexity through modular design.
3Productivity
If verification engines are composed in parallel to reduce verification time, then productivity is improved, but resource management complexity increases
Solution Approach 1:
The system introduces an intermediary resource management layer that coordinates parallel verification engines. This mediator handles resource allocation, scheduling, and conflict resolution between parallel engines, simplifying the management complexity while maintaining high productivity. The intermediary abstracts the complexity of parallel resource management from the individual verification engines.
Data Source
AI summary
A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.