Verification IP State Machine Modularity
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Solution Overview
Problem
Existing Verification Intellectual Property (VIP) architectures, such as UVM/OVM methodologies, face challenges in efficiently modifying functional logic for testing scenarios due to code redundancy and performance issues, particularly when dealing with complex or large-scale modifications.
Innovation Solution
The implementation of functional logics using state design pattern based finite state machines (FSMs) that communicate with each other, allowing for division of logic into multiple states, modification of state classes, and addition or removal of functionalities without altering the original implementation, thereby enhancing controllability, modularity, and observability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the entire functional logic is written inside the uvm_driver/ovm_driver, then the Verification IP can be implemented, but code redundancy increases and complexity increases when modifications are needed
Solution Approach 1:
The functional logic is segmented into separate callback modules that can be independently modified. Instead of having all logic in one driver class, the patent divides it into stimulus generation, transaction processing, and verification components that can be selectively overridden or modified through callbacks, reducing code redundancy while maintaining functionality.
Solution Approach 2:
The patent introduces callback mechanisms as intermediary layers between the driver and the functional logic. These callbacks act as mediators that allow external modification of specific logic portions without affecting the entire driver implementation, thus reducing complexity and redundancy when modifications are needed.
2Device complexity
If callbacks are used to achieve functionality modification, then code redundancy is avoided, but performance is degraded due to hierarchical access
Solution Approach 1:
The patent applies local quality by making callbacks optional and context-dependent. Critical performance-path logic uses direct methods without callback overhead, while logic requiring flexibility uses callbacks. This selective application optimizes performance by avoiding hierarchical access in time-critical paths while maintaining modularity where needed.
Solution Approach 2:
The system dynamically selects between direct method execution and callback-based execution based on the specific operation being performed. The driver architecture allows switching between optimized direct paths for performance-critical operations and flexible callback paths for modifiable logic, thus balancing performance and complexity requirements.
3Adaptability or versatility
If multiple callbacks are required for large functional logic modification, then functionality can be changed, but performance is increasingly degraded
Solution Approach 1:
The patent merges multiple related callbacks into consolidated logic blocks where possible. Instead of requiring separate callbacks for each small modification, the architecture allows combining multiple modification points into unified callback handlers, reducing the total number of hierarchical accesses while maintaining full functionality modification capability.
Solution Approach 2:
The callback system is designed with universal handlers that can perform multiple functions through configuration rather than requiring separate callbacks for each function. A single callback mechanism can handle stimulus generation, transaction processing, and verification modifications, reducing the number of hierarchical access points while maintaining adaptability.
Data Source
AI summary
A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.